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Searched refs:db_depth_control (Results 1 – 6 of 6) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_state.c410 unsigned db_depth_control, alpha_test_control, alpha_ref; in r600_create_dsa_state() local
425 db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) | in r600_create_dsa_state()
431 db_depth_control |= S_028800_STENCIL_ENABLE(1); in r600_create_dsa_state()
432 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ in r600_create_dsa_state()
433 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); in r600_create_dsa_state()
434 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); in r600_create_dsa_state()
435 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); in r600_create_dsa_state()
438 db_depth_control |= S_028800_BACKFACE_ENABLE(1); in r600_create_dsa_state()
439 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ in r600_create_dsa_state()
440db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); in r600_create_dsa_state()
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Devergreen_state.c422 unsigned db_depth_control, alpha_test_control, alpha_ref; in evergreen_create_dsa_state() local
437 db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) | in evergreen_create_dsa_state()
443 db_depth_control |= S_028800_STENCIL_ENABLE(1); in evergreen_create_dsa_state()
444 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ in evergreen_create_dsa_state()
445 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); in evergreen_create_dsa_state()
446 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); in evergreen_create_dsa_state()
447 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); in evergreen_create_dsa_state()
450 db_depth_control |= S_028800_BACKFACE_ENABLE(1); in evergreen_create_dsa_state()
451 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ in evergreen_create_dsa_state()
452db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); in evergreen_create_dsa_state()
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/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state.c1261 unsigned db_depth_control; in si_create_dsa_state() local
1273 db_depth_control = in si_create_dsa_state()
1279 db_depth_control |= S_028800_STENCIL_ENABLE(1); in si_create_dsa_state()
1280 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); in si_create_dsa_state()
1289 db_depth_control |= S_028800_BACKFACE_ENABLE(1); in si_create_dsa_state()
1290 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); in si_create_dsa_state()
1310 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); in si_create_dsa_state()
/third_party/mesa3d/src/amd/vulkan/
Dradv_pipeline.c1798 uint32_t db_depth_control = 0; in radv_pipeline_init_depth_stencil_state() local
1808 db_depth_control = S_028800_Z_ENABLE(ds_info->depthTestEnable ? 1 : 0) | in radv_pipeline_init_depth_stencil_state()
1815 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1); in radv_pipeline_init_depth_stencil_state()
1816 db_depth_control |= S_028800_STENCILFUNC(ds_info->front.compareOp); in radv_pipeline_init_depth_stencil_state()
1817 db_depth_control |= S_028800_STENCILFUNC_BF(ds_info->back.compareOp); in radv_pipeline_init_depth_stencil_state()
1821 pipeline->graphics.db_depth_control = db_depth_control; in radv_pipeline_init_depth_stencil_state()
Dradv_cmd_buffer.c1348 cmd_buffer->state.emitted_pipeline->graphics.db_depth_control != in radv_emit_graphics_pipeline()
1349 pipeline->graphics.db_depth_control) in radv_emit_graphics_pipeline()
1576 unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control; in radv_emit_depth_control() local
1579 db_depth_control &= C_028800_Z_ENABLE & in radv_emit_depth_control()
1588 db_depth_control |= S_028800_Z_ENABLE(d->depth_test_enable ? 1 : 0) | in radv_emit_depth_control()
1597 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, db_depth_control); in radv_emit_depth_control()
Dradv_private.h1810 unsigned db_depth_control; member