Searched refs:depth_bits (Results 1 – 9 of 9) sorted by relevance
| /third_party/mesa3d/src/mesa/drivers/dri/r200/ |
| D | radeon_screen.c | 809 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; in radeonInitScreen2() local
819 depth_bits[0] = 0; in radeonInitScreen2()
821 depth_bits[1] = 16; in radeonInitScreen2()
823 depth_bits[2] = 24; in radeonInitScreen2()
825 depth_bits[3] = 24; in radeonInitScreen2()
834 depth_bits, in radeonInitScreen2()
836 ARRAY_SIZE(depth_bits), in radeonInitScreen2()
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| /third_party/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_screen.c | 809 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; in radeonInitScreen2() local
819 depth_bits[0] = 0; in radeonInitScreen2()
821 depth_bits[1] = 16; in radeonInitScreen2()
823 depth_bits[2] = 24; in radeonInitScreen2()
825 depth_bits[3] = 24; in radeonInitScreen2()
834 depth_bits, in radeonInitScreen2()
836 ARRAY_SIZE(depth_bits), in radeonInitScreen2()
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| /third_party/mesa3d/src/mesa/drivers/dri/common/ |
| D | utils.c | 174 const uint8_t * depth_bits, const uint8_t * stencil_bits, in driCreateConfigs() argument
307 (depth_bits[k] || stencil_bits[k])) { in driCreateConfigs()
314 if ((depth_bits[k] + stencil_bits[k] == 16) != in driCreateConfigs()
346 modes->depthBits = depth_bits[k]; in driCreateConfigs()
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| D | utils.h | 44 const uint8_t * depth_bits, const uint8_t * stencil_bits,
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| /third_party/mesa3d/src/mesa/drivers/dri/nouveau/ |
| D | nouveau_screen.c | 58 const uint8_t depth_bits[] = { 0, 16, 24, 24 }; in nouveau_get_configs() local
76 depth_bits, stencil_bits, in nouveau_get_configs()
77 ARRAY_SIZE(depth_bits), in nouveau_get_configs()
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| /third_party/mesa3d/src/mesa/drivers/dri/i915/ |
| D | intel_screen.c | 1058 uint8_t depth_bits[4], stencil_bits[4]; in intel_screen_make_configs() local
1070 depth_bits[0] = 0; in intel_screen_make_configs()
1074 depth_bits[1] = 16; in intel_screen_make_configs()
1077 depth_bits[1] = 24; in intel_screen_make_configs()
1082 depth_bits, in intel_screen_make_configs()
1098 depth_bits[0] = 16; in intel_screen_make_configs()
1101 depth_bits[0] = 24; in intel_screen_make_configs()
1106 depth_bits, stencil_bits, 1, in intel_screen_make_configs()
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| /third_party/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_screen.c | 2246 uint8_t depth_bits[4], stencil_bits[4]; in brw_screen_make_configs() local
2265 depth_bits[0] = 0; in brw_screen_make_configs()
2270 depth_bits[num_depth_stencil_bits] = 16; in brw_screen_make_configs()
2275 depth_bits[num_depth_stencil_bits] = 24; in brw_screen_make_configs()
2280 depth_bits[num_depth_stencil_bits] = 24; in brw_screen_make_configs()
2286 depth_bits, in brw_screen_make_configs()
2306 depth_bits[0] = 16; in brw_screen_make_configs()
2309 depth_bits[0] = 24; in brw_screen_make_configs()
2312 depth_bits[0] = 0; in brw_screen_make_configs()
2316 depth_bits[0] = 24; in brw_screen_make_configs()
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| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_state.c | 246 unsigned depth_bits = in etna_set_framebuffer_state() local
270 cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f); in etna_set_framebuffer_state()
291 ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP); in etna_set_framebuffer_state()
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| /third_party/mesa3d/src/util/format/ |
| D | u_format.c | 354 int depth_bits; in util_get_depth_format_mrd() local
356 depth_bits = desc->channel[depth_channel].size; in util_get_depth_format_mrd()
357 mrd = 1.0 / ((1ULL << depth_bits) - 1); in util_get_depth_format_mrd()
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