Searched refs:desc_offset (Results 1 – 3 of 3) sorted by relevance
| /third_party/mesa3d/src/intel/vulkan/ |
| D | anv_nir_apply_pipeline_layout.c | 54 uint8_t desc_offset; member
205 surface_index = state->set[set].desc_offset; in descriptor_has_bti()
252 nir_ssa_def *desc_addr, unsigned desc_offset, in build_load_descriptor_mem() argument
262 nir_iadd_imm(b, nir_channel(b, desc_addr, 3), desc_offset); in build_load_descriptor_mem()
267 .align_offset = desc_offset % 8); in build_load_descriptor_mem()
273 nir_iadd_imm(b, nir_channel(b, desc_addr, 1), desc_offset); in build_load_descriptor_mem()
278 .align_offset = desc_offset % 8, in build_load_descriptor_mem()
328 assert(state->set[set].desc_offset < MAX_BINDING_TABLE_SIZE); in build_res_index()
329 set_idx = state->set[set].desc_offset; in build_res_index()
355 uint32_t surface_index = state->set[set].desc_offset; in build_res_index()
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| /third_party/mesa3d/src/freedreno/vulkan/ |
| D | tu_shader.c | 364 nir_ssa_def *desc_offset; in build_bindless() local
374 desc_offset = in build_bindless()
383 desc_offset = nir_iadd(b, desc_offset, in build_bindless()
387 return nir_bindless_resource_ir3(b, 32, desc_offset, .desc_set = set); in build_bindless()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_descriptors.c | 2181 unsigned desc_offset = si_get_image_slot(i) * 8; in si_emit_compute_shader_pointers() local
2186 desc_offset += 4; in si_emit_compute_shader_pointers()
2190 radeon_emit_array(&desc->list[desc_offset], num_sgprs); in si_emit_compute_shader_pointers()
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