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Searched refs:dst_access_mask (Results 1 – 13 of 13) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
Dbrw_eu_validate.c1372 uint64_t dst_access_mask[32], src0_access_mask[32], src1_access_mask[32]; in region_alignment_rules() local
1384 memset(dst_access_mask, 0, sizeof(dst_access_mask)); in region_alignment_rules()
1454 align1_access_mask(dst_access_mask, exec_size, element_size, subreg, in region_alignment_rules()
1459 unsigned dst_regs = registers_read(dst_access_mask); in region_alignment_rules()
1482 if (dst_access_mask[i] > 0x0000FFFF) { in region_alignment_rules()
1485 assert(dst_access_mask[i] != 0); in region_alignment_rules()
1534 if (dst_access_mask[i] > 0xFFFFFFFF) { in region_alignment_rules()
1537 assert(dst_access_mask[i] != 0); in region_alignment_rules()
1584 if ((dst_access_mask[i] > 0xFFFFFFFF) != \ in region_alignment_rules()
/third_party/mesa3d/src/virtio/vulkan/
Dvn_render_pass.h24 VkAccessFlags dst_access_mask; member
Dvn_render_pass.c104 att->dst_access_mask = in vn_render_pass_setup_present_src_barriers()
111 att->dst_access_mask = 0; in vn_render_pass_setup_present_src_barriers()
Dvn_command_buffer.c309 .dstAccessMask = att->dst_access_mask, in vn_present_src_attachment_to_image_memory_barrier()
/third_party/mesa3d/src/intel/vulkan/
Danv_pass.c45 VkAccessFlags2KHR dst_access_mask = in anv_render_pass_add_subpass_dep() local
50 anv_pipe_invalidate_bits_for_access_flags(device, dst_access_mask); in anv_render_pass_add_subpass_dep()
54 anv_pipe_invalidate_bits_for_access_flags(device, dst_access_mask); in anv_render_pass_add_subpass_dep()
/third_party/mesa3d/src/amd/vulkan/
Dradv_pass.c52 pass->end_barrier.dst_access_mask |= dep->dstAccessMask; in radv_render_pass_add_subpass_dep()
57 pass->subpasses[dst].start_barrier.dst_access_mask |= dep->dstAccessMask; in radv_render_pass_add_subpass_dep()
Dradv_meta_resolve_fs.c1080 barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT; in radv_cmd_buffer_resolve_subpass_fs()
1133 barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT; in radv_depth_stencil_resolve_subpass_fs()
Dradv_meta_resolve_cs.c797 barrier.dst_access_mask = VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT; in radv_cmd_buffer_resolve_subpass_cs()
Dradv_private.h2422 VkAccessFlags dst_access_mask; member
Dradv_cmd_buffer.c3993 radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask, fb->attachments[i]->image); in radv_emit_subpass_barrier()
3997 radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask, NULL); in radv_emit_subpass_barrier()
/third_party/mesa3d/src/freedreno/vulkan/
Dtu_pass.c112 dst_barrier->dst_access_mask |= dep->dstAccessMask; in tu_render_pass_add_subpass_dep()
Dtu_private.h1591 VkAccessFlags dst_access_mask; member
Dtu_cmd_buffer.c3119 vk2tu_access(barrier->dst_access_mask, false); in tu_subpass_barrier()