Searched refs:dstreg (Results 1 – 9 of 9) sorted by relevance
| /third_party/mesa3d/src/gallium/drivers/svga/svgadump/ |
| D | svga_shader_dump.c | 362 dump_dstreg(struct sh_dstreg dstreg, in dump_dstreg() argument
368 struct sh_dstreg dstreg; in dump_dstreg() member
373 …assert( (dstreg.modifier & (SVGA3DDSTMOD_SATURATE | SVGA3DDSTMOD_PARTIALPRECISION)) == dstreg.modi… in dump_dstreg()
375 if (dstreg.modifier & SVGA3DDSTMOD_SATURATE) in dump_dstreg()
377 if (dstreg.modifier & SVGA3DDSTMOD_PARTIALPRECISION) in dump_dstreg()
379 switch (dstreg.shift_scale) { in dump_dstreg()
405 u.dstreg = dstreg; in dump_dstreg()
407 if (dstreg.write_mask != SVGA3DWRITEMASK_ALL) { in dump_dstreg()
409 if (dstreg.write_mask & SVGA3DWRITEMASK_0) in dump_dstreg()
411 if (dstreg.write_mask & SVGA3DWRITEMASK_1) in dump_dstreg()
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| /third_party/mesa3d/src/gallium/drivers/llvmpipe/ |
| D | lp_state_fs_linear.c | 117 union { __m128i m128; uint ui[4]; } dstreg; in blend_premul() local
123 dstreg.m128 = util_sse2_blend_premul_4(*(const __m128i *)&src[i], in blend_premul()
125 _mm_storeu_si128((__m128i *)&dst[i], dstreg.m128); /* UNALIGNED WRITE */ in blend_premul()
131 dstreg.ui[j] = dst[i+j]; in blend_premul()
133 dstreg.m128 = util_sse2_blend_premul_4(*(const __m128i *)&src[i], in blend_premul()
134 dstreg.m128); in blend_premul()
136 dst[i] = dstreg.ui[i&3]; in blend_premul()
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| /third_party/mesa3d/src/mesa/state_tracker/ |
| D | st_atifs_to_nir.c | 400 unsigned dstreg = inst->DstReg[optype].Index - GL_REG_0_ATI; in compile_instruction() local
416 t->temps[dstreg] = nir_bcsel(t->b, in compile_instruction()
419 get_temp(t, dstreg)); in compile_instruction()
420 t->regs_written[t->current_pass][dstreg] = true; in compile_instruction()
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| /third_party/mesa3d/src/intel/isl/ |
| D | isl_tiled_memcpy.c | 127 __m128i srcreg, dstreg, agmask, ag, rb, br; in rgba8_copy_16_aligned_dst() local
136 dstreg = _mm_or_si128(ag, br); in rgba8_copy_16_aligned_dst()
138 _mm_store_si128((__m128i *)dst, dstreg); in rgba8_copy_16_aligned_dst()
144 __m128i srcreg, dstreg, agmask, ag, rb, br; in rgba8_copy_16_aligned_src() local
153 dstreg = _mm_or_si128(ag, br); in rgba8_copy_16_aligned_src()
155 _mm_storeu_si128((__m128i *)dst, dstreg); in rgba8_copy_16_aligned_src()
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| /third_party/mesa3d/src/mesa/swrast/ |
| D | s_atifragshader.c | 312 GLint dstreg; in execute_shader() local
525 dstreg = inst->DstReg[optype].Index; in execute_shader()
526 dstp = machine->Registers[dstreg - GL_REG_0_ATI]; in execute_shader()
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| /third_party/ffmpeg/libavfilter/x86/ |
| D | vf_hqdn3d.asm | 34 %macro LOAD 3 ; dstreg, x, bitdepth
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| /third_party/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_fragshader.c | 273 GLuint dstreg = inst->DstReg[optype].Index - GL_REG_0_ATI; in r200UpdateFSArith() local
280 SET_INST_2(opnum, optype) |= (dstreg + 1) << R200_TXC_OUTPUT_REG_SHIFT; in r200UpdateFSArith()
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| /third_party/mesa3d/src/gallium/frontends/d3d10umd/ |
| D | ShaderTGSI.c | 1455 struct ureg_dst dstreg = translate_dst_operand(&sx, &opcode.dst[0], in Shader_tgsi_translate() local
1476 ureg_MOV(ureg, dstreg, tsrc); in Shader_tgsi_translate()
1480 ureg_I2F(ureg, dstreg, tsrc); in Shader_tgsi_translate()
1498 struct ureg_dst dstregmasked = ureg_writemask(dstreg, 1 << i); in Shader_tgsi_translate()
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| /third_party/mesa3d/src/intel/tools/ |
| D | i965_gram.y | 504 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
1515 dstreg dstregion writemask reg_type
1571 dstreg:
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