| /third_party/mesa3d/src/asahi/compiler/ |
| D | agx_opcodes.py | 29 def __init__(self, name, dests, srcs, imms, is_float, can_eliminate, encoding_16, encoding_32): argument
33 self.imms = imms
60 def op(name, encoding_32, dests = 1, srcs = 0, imms = [], is_float = False, can_eliminate = True, e… argument
64 … opcodes[name] = Opcode(name, dests, srcs, imms, is_float, can_eliminate, encoding_16, encoding_32)
164 imms = [IMM])
168 srcs = 2, imms = [SHIFT])
172 srcs = 3, imms = [SHIFT])
176 srcs = 3, imms = [BFI_MASK])
180 srcs = 3, imms = [BFI_MASK])
188 srcs = 4, imms = [ICOND])
[all …]
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| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_dataflow_swizzles.c | 106 float imms[4] = {0.0f, 0.0f, 0.0f, 0.0f}; in try_rewrite_constant() local
389 imms[new_swz] = 0.0f; in try_rewrite_constant()
393 imms[new_swz] = -0.5f; in try_rewrite_constant()
395 imms[new_swz] = 0.5f; in try_rewrite_constant()
400 imms[new_swz] = -1.0f; in try_rewrite_constant()
402 imms[new_swz] = 1.0f; in try_rewrite_constant()
406 imms[new_swz] = rc_get_constant_value(c, reg->Index, in try_rewrite_constant()
412 imms); in try_rewrite_constant()
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| /third_party/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_build_util.cpp | 49 memset(imms, 0, sizeof(imms)); in init()
61 while (imms[pos]) in addImmediate()
63 imms[pos] = imm; in addImmediate()
375 while (imms[pos] && imms[pos]->reg.data.u32 != u) in mkImm()
378 ImmediateValue *imm = imms[pos]; in mkImm()
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| D | nv50_ir_build_util.h | 198 ImmediateValue *imms[NV50_IR_BUILD_IMM_HT_SIZE]; variable
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| /third_party/mesa3d/src/gallium/auxiliary/translate/ |
| D | translate_sse.c | 473 unsigned imms[2] = { 0, 0x3f800000 }; in translate_attr_convert() local
682 imms[swizzle[0] - PIPE_SWIZZLE_0]); in translate_attr_convert()
692 imms[swizzle[1] - PIPE_SWIZZLE_0]); in translate_attr_convert()
710 imms[swizzle[2] - PIPE_SWIZZLE_0]); in translate_attr_convert()
720 imms[swizzle[3] - PIPE_SWIZZLE_0]); in translate_attr_convert()
742 unsigned imms[2] = { 0, 1 }; in translate_attr_convert() local
798 imms[1] = in translate_attr_convert()
826 imms[swizzle[1] - PIPE_SWIZZLE_0]); in translate_attr_convert()
833 (imms[swizzle[1] - PIPE_SWIZZLE_0] << 16) | in translate_attr_convert()
834 imms[swizzle[0] - PIPE_SWIZZLE_0]); in translate_attr_convert()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 297 unsigned imms = val & 0x3f; in decodeLogicalImmediate() local
300 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in decodeLogicalImmediate()
304 unsigned S = imms & (size - 1); in decodeLogicalImmediate()
325 unsigned imms = val & 0x3f; in isValidDecodeLogicalImmediate() local
329 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in isValidDecodeLogicalImmediate()
333 unsigned S = imms & (size - 1); in isValidDecodeLogicalImmediate()
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| D | AArch64InstPrinter.cpp | 122 int64_t imms = Op3.getImm(); in printInst() local
123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
125 shift = 31 - imms; in printInst()
126 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
127 ((imms + 1 == immr))) { in printInst()
129 shift = 63 - imms; in printInst()
130 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
133 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { in printInst()
136 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { in printInst()
139 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) { in printInst()
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| /third_party/mesa3d/src/panfrost/bifrost/valhall/ |
| D | valhall.py | 261 imms = [build_imm(imm) for imm in el.findall('imm')]
270 …instr = Instruction(name, opcode, opcode2, srcs = sources, dests = dests, immediates = imms, modif…
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| /third_party/mesa3d/src/gallium/frontends/d3d10umd/ |
| D | ShaderTGSI.c | 213 struct ureg_src imms; member
1025 reg = sx->imms; in translate_src_operand()
1030 reg = sx->imms; in translate_src_operand()
1033 sx->imms, in translate_src_operand()
1425 sx.imms = in Shader_tgsi_translate()
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| /third_party/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_soa.c | 2988 LLVMValueRef imms[4]; in lp_emit_immediate_soa() local
2995 imms[i] = in lp_emit_immediate_soa()
3005 imms[i] = LLVMConstBitCast(tmp, bld_base->base.vec_type); in lp_emit_immediate_soa()
3012 imms[i] = LLVMConstBitCast(tmp, bld_base->base.vec_type); in lp_emit_immediate_soa()
3018 imms[i] = bld_base->base.undef; in lp_emit_immediate_soa()
3032 LLVMBuildStore(builder, imms[i], imm_ptr); in lp_emit_immediate_soa()
3041 bld->immediates[bld->num_immediates][i] = imms[i]; in lp_emit_immediate_soa()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARM.td | 404 "32-bit imms">;
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| D | ARMInstrThumb.td | 1691 // Two piece imms.
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 2542 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
2543 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
2548 bits<6> imms;
2553 let Inst{15-10} = imms;
2562 // imms<5> and immr<5> must be zero, else ReservedValue().
2576 imm_type:$imms),
2577 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
2582 bits<6> imms;
2587 let Inst{15-10} = imms;
2596 // imms<5> and immr<5> must be zero, else ReservedValue().
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| D | SVEInstrFormats.td | 1305 : I<(outs ZPR64:$Zd), (ins logical_imm64:$imms),
1306 asm, "\t$Zd, $imms",
1310 bits<13> imms;
1312 let Inst{17-5} = imms;
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_exec.c | 1169 float4 *imms = REALLOC(mach->Imms, mach->ImmsReserved, newReserved * sizeof(float4)); in tgsi_exec_machine_bind_shader() local
1170 if (imms) { in tgsi_exec_machine_bind_shader()
1172 mach->Imms = imms; in tgsi_exec_machine_bind_shader()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCCodeEmitter.inc | 9893 // op: imms
9916 // op: imms
9994 // op: imms
10016 // op: imms
14332 // op: imms
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.1.0.rst | 669 - pan/bi: Fix bi_get_immediate with multiple imms
|
| D | 20.3.0.rst | 614 - pan/bi: Use canonical syntax for registers/uniforms/imms
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenSubtargetInfo.inc | 311 …{ "no-movt", "Don't use movt/movw pairs for 32-bit imms", ARM::FeatureNoMovt, { { { 0x0ULL, 0x0ULL…
|