Searched refs:is_mec (Results 1 – 2 of 2) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/ |
| D | si_cmd_buffer.c | 838 si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, bool is_mec, in si_cs_emit_write_event_eop() argument
846 unsigned is_gfx8_mec = is_mec && chip_class < GFX9; in si_cs_emit_write_event_eop()
859 if (chip_class == GFX9 && !is_mec) { in si_cs_emit_write_event_eop()
885 if (is_mec) { in si_cs_emit_write_event_eop()
940 si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl) in si_emit_acquire_mem() argument
942 if (is_mec || is_gfx9) { in si_emit_acquire_mem()
944 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) | PKT3_SHADER_TYPE_S(is_mec)); in si_emit_acquire_mem()
963 uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, in gfx10_cs_emit_cache_flush() argument
1120 !is_mec) { in gfx10_cs_emit_cache_flush()
1139 uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, in si_cs_emit_cache_flush() argument
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| D | radv_private.h | 1530 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, bool is_mec,
1538 uint32_t *fence_ptr, uint64_t va, bool is_mec,
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