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/third_party/skia/third_party/externals/swiftshader/third_party/marl/src/
Dosfiber_asm_aarch64.S111 ldr x16, [x7, #MARL_REG_r16]
112 ldr x17, [x7, #MARL_REG_r17]
113 ldr x18, [x7, #MARL_REG_r18]
116 ldr x19, [x7, #MARL_REG_r19]
117 ldr x20, [x7, #MARL_REG_r20]
118 ldr x21, [x7, #MARL_REG_r21]
119 ldr x22, [x7, #MARL_REG_r22]
120 ldr x23, [x7, #MARL_REG_r23]
121 ldr x24, [x7, #MARL_REG_r24]
122 ldr x25, [x7, #MARL_REG_r25]
[all …]
Dosfiber_asm_arm.S54 ldr r12, [r3, #MARL_REG_r12]
57 ldr r4, [r3, #MARL_REG_r4]
58 ldr r5, [r3, #MARL_REG_r5]
59 ldr r6, [r3, #MARL_REG_r6]
60 ldr r7, [r3, #MARL_REG_r7]
61 ldr r8, [r3, #MARL_REG_r8]
62 ldr r9, [r3, #MARL_REG_r9]
63 ldr r10, [r3, #MARL_REG_r10]
64 ldr r11, [r3, #MARL_REG_r11]
67 ldr r0, [r3, #MARL_REG_r0]
[all …]
/third_party/ffmpeg/libavcodec/arm/
Dmpegaudiodsp_fixed_armv6.S27 ldr \t1, [\w, #4*\offs]
28 ldr \t2, [\p, #4]!
31 ldr \t3, [\w, #4*64*\i+4*\offs]
32 ldr \t4, [\p, #4*64*\i]
35 ldr \t1, [\w, #4*64*(\i+1)+4*\offs]
36 ldr \t2, [\p, #4*64*(\i+1)]
40 ldr \t3, [\w, #4*64*7+4*\offs]
41 ldr \t4, [\p, #4*64*7]
64 ldr r4, [sp, #40] @ incr
66 ldr r8, [r2] @ sum:low
[all …]
Dme_cmp_armv6.S24 ldr r0, [sp]
29 ldr r8, [r2]
31 ldr r9, [r2, #4]
34 ldr r8, [r2, #8]
37 ldr r9, [r2, #12]
45 ldr r8, [r2]
53 ldr r12, [sp]
60 ldr r8, [r2]
61 ldr r9, [r2, #4]
63 ldr r4, [r1]
[all …]
Dhpeldsp_armv6.S43 ldr r5, [r1, #4]
44 ldr r6, [r1, #8]
45 ldr r7, [r1, #12]
48 ldr r9, [r1, #4]
50 ldr r10, [r1, #8]
51 ldr r11, [r1, #12]
65 ldr r5, [r1, #4]
67 ldr r7, [r1, #4]
84 ldr r4, [r1]
86 ldr r5, [r1, #4]
[all …]
Dsimple_idct_armv6.S54 ldr lr, =W46 /* lr = W4 | (W6 << 16) */
58 ldr ip, =W13 /* ip = W1 | (W3 << 16) */
59 ldr r10,=W57 /* r10 = W5 | (W7 << 16) */
65 ldr lr, [r0, #12] /* lr = row[7,5] */
72 ldr r3, =W42n /* r3 = -W4 | (-W2 << 16) */
74 ldr r2, [r0, #4] /* r2 = row[6,4] */
76 ldr ip, =W46 /* ip = W4 | (W6 << 16) */
95 ldr lr, =W46 /* lr = W4 | (W6 << 16) */
96 ldr r10,=W57 /* r10 = W5 | (W7 << 16) */
100 ldr ip, =W13 /* ip = W1 | (W3 << 16) */
[all …]
Dflacdsp_arm.S24 ldr r12, [sp]
26 ldr r1, [r1]
28 ldr lr, [r0], #4
45 ldr r2, [r0]
52 ldr r12, [sp]
78 ldr r5, [r0]
89 ldr r12, [sp]
103 ldr r7, [r0], #4
104 ldr r9, [r1], #4
117 ldr r7, [r0], #4
[all …]
Djrevdct_arm.S70 ldr r5, [lr, # 0]
71 ldr r6, [lr, # 4]
72 ldr r3, [lr, # 8]
73 ldr r4, [lr, #12]
85 ldr r3, [r11, #FIX_0_541196100_ID]
87 ldr r5, [r11, #FIX_M_1_847759065_ID]
89 ldr r3, [r11, #FIX_0_765366865_ID]
110 ldr r9, [r11, #FIX_1_175875602_ID]
112 ldr r10, [r11, #FIX_M_0_899976223_ID]
114 ldr r9, [r11, #FIX_M_2_562915447_ID]
[all …]
/third_party/mindspore/mindspore/ccsrc/backend/kernel_compiler/cpu/nnacl/assembly/arm32/
DConvDwFp32Center.S38 ldr r4, [sp] // height
46 ldr r1, [sp, #-44] // src_w, src_h = src
47 ldr r5, [sp, #4] // width
48 ldr r0, [sp, #-48] // dst_w, dst_h = dst
52 ldr r11, [sp, #28] // in_sw_step
54 ldr r2, [sp, #-40] // weight_kh, weight
55 ldr r6, [sp, #8] // kernel_h
61 ldr r7, [sp, #12] // kernel_w
64 ldr r12, [sp, #36] //in_kw_step
82 ldr r12, [sp, #32] // in_kh_step
[all …]
DDeconvDwInt8Center.S35 ldr r10, [sp, #80] // in_kw_step
36 ldr r11, [sp, #76] // in_kh_step
39 ldr r0, [sp] // dst_w
40 ldr r1, [sp, #4] // src_w
41 ldr r4, [sp, #48] // width
44 ldr r2, [sp, #8] // weight_kh
45 ldr r5, [sp, #52] // kernel_h
49 ldr r12, [sp, #56] // kernel_w
61 ldr r12, [sp, #72]
63 ldr r8, [sp, #64]
[all …]
DDeconvDwFp32Center.S35 ldr r10, [sp, #80] // in_kw_step
36 ldr r11, [sp, #76] // in_kh_step
39 ldr r0, [sp] // dst_w
40 ldr r1, [sp, #4] // src_w
41 ldr r4, [sp, #48] // width
44 ldr r2, [sp, #8] // weight_kh
45 ldr r5, [sp, #52] // kernel_h
49 ldr r12, [sp, #56] // kernel_w
61 ldr r12, [sp, #72]
63 ldr r8, [sp, #64]
[all …]
DConvDwInt8Center.S39 ldr lr, [sp, #168]
42 ldr lr, [sp, #204]
45 ldr lr, [sp, #240]
50 ldr r1, [sp, #-36]
52 ldr r1, [sp, #44]
54 ldr r1, [sp, #48]
56 ldr r1, [sp, #52]
59 ldr r11, [sp, #28]
60 ldr r4, [sp]
62 ldr r1, [sp, #-44]
[all …]
DMatmulInt8.S34 ldr r4, [sp] // col
35 ldr r7, [sp, #40] // output stride
37 ldr r10, [sp, #44]
40 ldr r6, [sp, #8] // load intpu_sums ptr if per_channel
45 ldr r0, [sp, #-52] // reload a ptr
46 ldr r3, [sp, #-40] // reset row counter
47 ldr r10, [sp, #44]
50 ldr r6, [sp, #8] // reload intpu_sums ptr if per_tensor
55 ldr r1, [sp, #-48] // reload b ptr
56 ldr r5, [sp, #4] // reset deep16
[all …]
DConvDw3x3Int8BorderPixel.S42 ldr r4, [sp]
43 ldr r5, [sp, #4]
44 ldr r6, [sp, #8]
45 ldr r7, [sp, #12]
46 ldr r8, [sp, #16]
50 ldr r10, [sp, #24] // out_zp
52 ldr r10, [sp, #28] // out_multiplier
54 ldr r10, [sp, #32] // left_shift
56 ldr r10, [sp, #36] // right_shift
58 ldr r10, [sp, #40] // acc_min
[all …]
DIndirectGemmInt8_2x4.S47 ldr r4, [sp]
48 ldr r5, [sp, #4]
49 ldr r6, [sp, #8]
50 ldr r7, [sp, #12]
157 ldr lr, [sp, #44]
160 ldr r10, [sp, #16]
161 ldr lr, [sp, #48]
164 ldr lr, [sp, #52]
183 ldr lr, [sp, #48]
186 ldr lr, [sp, #36]
[all …]
DMatmulWinogradFp32.S36 ldr r4, [sp, #4] // n
37 ldr r5, [sp, #8] // in_channel
38 ldr r6, [sp] // k
46 ldr r7, [sp, #4] // n
47 ldr r8, [sp, #-52] // matrix_b
49 ldr r0, [sp, #4] // n
50 ldr r1, [sp, #-44] // m
55 ldr r1, [sp, #12]
59 ldr r10, [sp, #8] // in_channel
60 ldr r9, [sp, #-56] // src
[all …]
/third_party/optimized-routines/string/arm/
Dmemcpy.S164 ldr tmp1, [src, #-60] /* 15 words to go. */
167 ldr tmp1, [src, #-56] /* 14 words to go. */
169 ldr tmp1, [src, #-52]
172 ldr tmp1, [src, #-48] /* 12 words to go. */
174 ldr tmp1, [src, #-44]
177 ldr tmp1, [src, #-40] /* 10 words to go. */
179 ldr tmp1, [src, #-36]
182 ldr tmp1, [src, #-32] /* 8 words to go. */
184 ldr tmp1, [src, #-28]
187 ldr tmp1, [src, #-24] /* 6 words to go. */
[all …]
/third_party/openssl/crypto/aes/asm/arm32/
Daes-armv4.S211 ldr r0,[r12,#0]
212 ldr r1,[r12,#4]
213 ldr r2,[r12,#8]
214 ldr r3,[r12,#12]
224 ldr r12,[sp],#4 @ pop out
282 ldr r12,[r11,#240-16]
294 ldr r4,[r10,r7,lsl#2] @ Te3[s0>>0]
296 ldr r5,[r10,r8,lsl#2] @ Te2[s0>>8]
298 ldr r6,[r10,r9,lsl#2] @ Te1[s0>>16]
300 ldr r0,[r10,r0,lsl#2] @ Te0[s0>>24]
[all …]
/third_party/openssl/crypto/sha/asm/arm32/
Dsha1-armv4-large.S19 ldr r12,.LOPENSSL_armcap
20 ldr r12,[r3,r12] @ OPENSSL_armcap_P
22 ldr r12,[r12]
33 ldr r8,.LK_00_19
52 ldr r9,[r1],#4 @ handles unaligned
77 ldr r9,[r1],#4 @ handles unaligned
102 ldr r9,[r1],#4 @ handles unaligned
127 ldr r9,[r1],#4 @ handles unaligned
152 ldr r9,[r1],#4 @ handles unaligned
185 ldr r9,[r1],#4 @ handles unaligned
[all …]
/third_party/openssl/crypto/sha/asm/arm64/
Dkeccak1600-armv8.S145 ldr x27,[sp,#16]
149 ldr x30,[x27],#8 // Iota[i++]
200 ldr x30,[sp,#24]
232 ldr x24,[x26,#16*12]
236 ldr x26,[sp,#32]
295 ldr x24,[x26,#16*12]
304 ldr x26,[x27],#8 // *inp++
311 ldr x26,[x27],#8 // *inp++
317 ldr x26,[x27],#8 // *inp++
324 ldr x26,[x27],#8 // *inp++
[all …]
/third_party/musl/src/ldso/arm/
Dtlsdesc.S8 ldr r0,[r0]
16 ldr r1,[r0]
17 ldr r2,[r1,#4] // r2 = offset
18 ldr r1,[r1] // r1 = modid
24 ldr r0,1f
26 ldr r0,[r0]
39 ldr r3,[r0,#-4] // r3 = dtv
40 ldr ip,[r3,r1,LSL #2]
/third_party/openssl/crypto/bn/asm/arm32/
Darmv4-mont.S23 ldr ip,[sp,#4] @ load num
29 ldr r2,.LOPENSSL_armcap
30 ldr r0,[r0,r2]
32 ldr r0,[r0]
60 ldr r8,[r0,#14*4] @ &n0
61 ldr r2,[r2] @ bp[0]
62 ldr r5,[r1],#4 @ ap[0],ap++
63 ldr r6,[r3],#4 @ np[0],np++
64 ldr r8,[r8] @ *n0
75 ldr r5,[r1],#4 @ ap[j],ap++
[all …]
/third_party/openssl/crypto/ec/asm/arm32/
Decp_nistz256-armv4.S2425 ldr r4,[r1,#0]
2426 ldr r5,[r1,#4]
2427 ldr r6,[r1,#8]
2429 ldr r7,[r1,#12]
2431 ldr r8,[r1,#16]
2433 ldr r9,[r1,#20]
2435 ldr r10,[r1,#24]
2437 ldr r11,[r1,#28]
2468 ldr r4,[r1,#0]
2469 ldr r5,[r1,#4]
[all …]
/third_party/libffi/src/aarch64/
Dwin64_armasm.S222 ldr PTR_REG(2), [x17, #FFI_TRAMPOLINE_CLOSURE_OFFSET+PTR_SIZE*2] /* load user_data */
244 ldr x0, [x3] /* INT64 */
258 ldr s3, [x3, #12] /* S4 */
260 ldr s2, [x3, #8] /* S3 */
264 ldr s0, [x3] /* S1 */
266 ldr d3, [x3, #24] /* D4 */ define
268 ldr d2, [x3, #16] /* D3 */ define
272 ldr d0, [x3] /* D1 */ define
274 ldr q3, [x3, #48] /* Q4 */
276 ldr q2, [x3, #32] /* Q3 */
[all …]
/third_party/ffmpeg/libswscale/arm/
Dyuv2rgb_neon.S101 ldr r4, [sp, #104] @ r4 = srcY
102 ldr r5, [sp, #108] @ r5 = linesizeY
103 ldr r6, [sp, #112] @ r6 = srcC
104 ldr r7, [sp, #116] @ r7 = linesizeC
105 ldr r8, [sp, #120] @ r8 = table
106 ldr r9, [sp, #124] @ r9 = y_offset
107 ldr r10,[sp, #128] @ r10 = y_coeff
126 ldr r4, [sp, #104] @ r4 = srcY
127 ldr r5, [sp, #108] @ r5 = linesizeY
128 ldr r6, [sp, #112] @ r6 = srcU
[all …]

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