| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_lower_alu.c | 45 nir_ssa_def *lowered = NULL; in lower_alu_instr() local
69 lowered = nir_ssa_for_alu_src(b, instr, 0); in lower_alu_instr()
72 lowered = nir_ior(b, in lower_alu_instr()
73 nir_iand(b, nir_ushr(b, lowered, c1), c55555555), in lower_alu_instr()
74 nir_ishl(b, nir_iand(b, lowered, c55555555), c1)); in lower_alu_instr()
77 lowered = nir_ior(b, in lower_alu_instr()
78 nir_iand(b, nir_ushr(b, lowered, c2), c33333333), in lower_alu_instr()
79 nir_ishl(b, nir_iand(b, lowered, c33333333), c2)); in lower_alu_instr()
82 lowered = nir_ior(b, in lower_alu_instr()
83 nir_iand(b, nir_ushr(b, lowered, c4), c0f0f0f0f), in lower_alu_instr()
[all …]
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| D | nir_lower_bit_size.c | 297 nir_phi_instr *lowered[2] = { in split_phi() local
312 nir_phi_instr_add_src(lowered[0], src->pred, nir_src_for_ssa(x)); in split_phi()
313 nir_phi_instr_add_src(lowered[1], src->pred, nir_src_for_ssa(y)); in split_phi()
316 nir_ssa_dest_init(&lowered[0]->instr, &lowered[0]->dest, in split_phi()
318 nir_ssa_dest_init(&lowered[1]->instr, &lowered[1]->dest, in split_phi()
322 nir_builder_instr_insert(b, &lowered[0]->instr); in split_phi()
323 nir_builder_instr_insert(b, &lowered[1]->instr); in split_phi()
326 nir_ssa_def *merged = nir_pack_64_2x32_split(b, &lowered[0]->dest.ssa, &lowered[1]->dest.ssa); in split_phi()
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| D | README | 13 (and later, from an AST), but for the most part, they will be lowered to
98 has a sampler dereference field used just like in GLSL IR, this gets lowered to
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| /third_party/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_lowering_gv100.cpp | 249 bool lowered = false; in visit() local
261 lowered = handleLOP2(i); in visit()
264 lowered = handleNOT(i); in visit()
268 lowered = handleShift(i); in visit()
275 lowered = handleSET(i); in visit()
278 lowered = handleCMP(i); in visit()
281 lowered = handlePREEX2(i); in visit()
285 lowered = handleIMUL(i); in visit()
289 lowered = handleIMAD_HIGH(i); in visit()
292 lowered = handleSHFL(i); in visit()
[all …]
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| /third_party/skia/third_party/externals/spirv-cross/shaders-msl-no-opt/packing/ |
| D | struct-alignment.comp | 14 // <- We expect 4 bytes of padding here since MSL alignment of Foo must be lowered to 4.
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| /third_party/mesa3d/src/compiler/glsl/ |
| D | lower_jumps.cpp | 642 ir_loop_jump* lowered = 0; in visit() local
643 lowered = new(ir) ir_loop_jump(ir_loop_jump::jump_break); in visit()
649 jumps[lower]->replace_with(lowered); in visit()
650 jumps[lower] = lowered; in visit()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallingConv.td | 23 /// For example, this is true for i32's that were lowered from soft-float.
190 // legal and is lowered to i128 which is further lowered to a pair of i64's.
327 // f128 is not legal and is lowered to i128 which is further lowered to a pair
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| D | Relocation.txt | 31 2. Generic address nodes are lowered to some combination of target
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| D | MSA.txt | 4 Intrinsics are lowered to SelectionDAG nodes where possible in order to enable
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiCallingConv.td | 45 // been lowered to 2 32-bit values.
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceInstX86.def | 10 // This file defines properties of lowered x86 instructions in the
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| D | IceInstX8632.def | 10 // This file defines properties of lowered x86-32 instructions in the
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| /third_party/mesa3d/src/microsoft/compiler/ |
| D | dxil_nir.c | 1054 nir_phi_instr *lowered = nir_phi_instr_create(b->shader); in cast_phi() local
1072 nir_phi_instr_add_src(lowered, src->pred, nir_src_for_ssa(cast)); in cast_phi()
1075 nir_ssa_dest_init(&lowered->instr, &lowered->dest, in cast_phi()
1079 nir_builder_instr_insert(b, &lowered->instr); in cast_phi()
1082 nir_ssa_def *result = nir_build_alu(b, downcast_op, &lowered->dest.ssa, NULL, NULL, NULL); in cast_phi()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.3.2.rst | 92 - nir/lower_io: include the variable access in the lowered intrinsic
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| D | 10.3.3.rst | 103 - radeonsi: fix incorrect index buffer max size for lowered 8-bit
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| /third_party/mbedtls/tests/suites/ |
| D | test_suite_net.function | 98 * opened before the limit was lowered (which is something an application
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/docs/ |
| D | REGALLOC.rst | 44 which case the lowering is relatively simple. But if the lowered instruction
47 temporary in the lowered instruction.
311 lowered assignments, and can lead to worse register allocation decisions. As a
324 are prevented from having the same register. Swapping the order of lowered
330 pass limited to the new lowered assignments.
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| /third_party/python/Doc/library/ |
| D | resource.rst | 35 limit. The soft limit is the current limit, and may be lowered or raised by a
37 limit can be lowered to any value greater than the soft limit, but not raised.
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 7 SSE Variable shift can be custom lowered to something like this, which uses a
89 Currently, the select is being lowered, which prevents the dag combiner from
479 Note: this is not a code quality issue; the custom lowered code happens to be
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| D | README-X86-64.txt | 73 lowered return value, and it would free non-C frontends from a
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | README.txt | 127 If the i64 division is lowered to a libcall, then a safe point will (must)
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| /third_party/mesa3d/docs/gallium/ |
| D | screen.rst | 588 Otherwise, alpha test will be lowered to a comparison and discard_if in the
603 …ed. This also means that the gl_Position value is modified and should be lowered for transform fee…
604 …Additionally, the gl_PointSize has been modified and its value should be lowered for transform fee…
617 …he GL frontend. NIR drivers with the cap unavailable will have GL_CLAMP lowered to txd/txl with a…
695 If unsupported, half precision ops need to be lowered to full precision.
706 Note that 16-bit constants are not lowered to uniforms in GLSL.
734 cost than this value should be lowered by gallium frontends for better
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | Attributes.td | 196 /// this attribute will always be lowered with hardening enabled.
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| D | IntrinsicsPowerPC.td | 578 // vpkuhum is lowered to a shuffle.
582 // vpkuwum is lowered to a shuffle.
586 // vpkudum is lowered to a shuffle.
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| /third_party/mesa3d/src/amd/compiler/ |
| D | README.md | 48 They eventually get lowered to real hardware instructions.
97 Most pseudo instructions are lowered to actual machine instructions.
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