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Searched refs:msfign (Results 1 – 8 of 8) sorted by relevance

/third_party/mesa3d/src/broadcom/qpu/
Dqpu_instr.h349 enum v3d_qpu_msfign msfign; member
402 const char *v3d_qpu_msfign_name(enum v3d_qpu_msfign msfign);
Dqpu_pack.c1365 uint32_t msfign = QPU_GET_FIELD(packed_instr, V3D_QPU_BRANCH_MSFIGN); in v3d_qpu_instr_unpack_branch() local
1366 if (msfign == 3) in v3d_qpu_instr_unpack_branch()
1368 instr->branch.msfign = msfign; in v3d_qpu_instr_unpack_branch()
1473 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign, in v3d_qpu_instr_pack_branch()
1488 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign, in v3d_qpu_instr_pack_branch()
Dqpu_instr.c245 v3d_qpu_msfign_name(enum v3d_qpu_msfign msfign) in v3d_qpu_msfign_name() argument
247 switch (msfign) { in v3d_qpu_msfign_name()
Dqpu_disasm.c275 append(disasm, "%s", v3d_qpu_msfign_name(instr->branch.msfign)); in v3d_qpu_disasm_branch()
/third_party/mesa3d/src/broadcom/compiler/
Dvir_dump.c314 fprintf(stderr, "%s", v3d_qpu_msfign_name(instr->branch.msfign)); in vir_dump_inst()
Dqpu_schedule.c1113 inst->branch.msfign != V3D_QPU_MSFIGN_NONE && in choose_instruction_to_schedule()
1838 inst->qpu.branch.msfign == V3D_QPU_MSFIGN_NONE || in emit_branch()
Dnir_to_vir.c3378 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P; in ntq_emit_uniform_if()
3419 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P; in ntq_emit_uniform_if()
3688 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P; in ntq_emit_nonuniform_loop()
Dvir.c399 inst->qpu.branch.msfign = V3D_QPU_MSFIGN_NONE; in vir_branch_inst()