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Searched refs:num_banks (Results 1 – 11 of 11) sorted by relevance

/third_party/mesa3d/src/amd/addrlib/src/chip/r800/
Dsi_gb_reg.h112 unsigned int num_banks : 2; member
122 unsigned int num_banks : 2; member
135 unsigned int num_banks : 2; member
150 unsigned int num_banks : 2; member
/third_party/libdrm/radeon/
Dradeon_surface.c103 uint32_t num_banks; member
240 surf_man->hw_info.num_banks = 4; in r6_init_hw_info()
243 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
246 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
371 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) / in r6_surface_init_2d()
373 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); in r6_surface_init_2d()
383 surf_man->hw_info.num_banks * in r6_surface_init_2d()
525 surf_man->hw_info.num_banks = 4; in eg_init_hw_info()
528 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
531 surf_man->hw_info.num_banks = 16; in eg_init_hw_info()
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/third_party/mesa3d/src/amd/vulkan/
Dradv_radeon_winsys.h138 unsigned num_banks; member
Dradv_image.c435 surface->u.legacy.num_banks = md->u.legacy.num_banks; in radv_patch_surface_from_metadata()
1288 metadata->u.legacy.num_banks = surface->u.legacy.num_banks; in radv_init_metadata()
/third_party/mesa3d/src/amd/common/
Dac_surface.h120 unsigned num_banks : 5; /* max 16 */ member
Dac_surface.c856 surf->u.legacy.num_banks = csio->pTileInfo->banks; in gfx6_surface_settings()
1113 AddrTileInfoIn.banks = surf->u.legacy.num_banks; in gfx6_compute_surface()
2535 surf->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in ac_surface_set_bo_metadata()
2590 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks) - 1); in ac_surface_get_bo_metadata()
2976 surf->u.legacy.num_banks, surf->u.legacy.mtilea, in ac_surface_print_info()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_texture.c288 metadata->u.legacy.num_banks = surface->u.legacy.num_banks; in r600_texture_init_metadata()
304 surf->u.legacy.num_banks = metadata->u.legacy.num_banks; in r600_surface_import_metadata()
841 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea, in r600_print_texture_info()
/third_party/mesa3d/src/gallium/drivers/radeon/
Dradeon_winsys.h232 unsigned num_banks; member
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_bo.c940 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks) - 1); in radv_amdgpu_winsys_bo_set_metadata()
986 md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in radv_amdgpu_winsys_bo_get_metadata()
/third_party/mesa3d/src/amd/addrlib/src/r800/
Dciaddrlib.cpp1748 pCfg->banks = 1 << (gbTileMode.f.num_banks + 1); in ReadGbMacroTileCfg()
Dsiaddrlib.cpp3084 pCfg->info.banks = 1 << (gbTileMode.f.num_banks + 1); in ReadGbTileMode()