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Searched refs:num_sgprs (Results 1 – 22 of 22) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shader_llvm_gs.c554 unsigned num_sgprs, num_vgprs; in si_llvm_build_gs_prolog() local
563 num_sgprs = 8 + SI_NUM_VS_STATE_RESOURCE_SGPRS; in si_llvm_build_gs_prolog()
566 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2; in si_llvm_build_gs_prolog()
570 for (unsigned i = 0; i < num_sgprs; ++i) { in si_llvm_build_gs_prolog()
577 returns[num_sgprs + i] = ctx->ac.f32; in si_llvm_build_gs_prolog()
581 si_llvm_create_func(ctx, "gs_prolog", returns, num_sgprs + num_vgprs, 0); in si_llvm_build_gs_prolog()
588 for (unsigned i = 0; i < num_sgprs; i++) { in si_llvm_build_gs_prolog()
593 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i); in si_llvm_build_gs_prolog()
595 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, ""); in si_llvm_build_gs_prolog()
601 {.used = true, .arg_index = num_sgprs}, {.used = true, .arg_index = num_sgprs + 1}, in si_llvm_build_gs_prolog()
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Dsi_shader.c723 unsigned num_sgprs = shader->selector->info.base.image_buffers & (1 << i) ? 4 : 8; in si_init_shader_args() local
725 while (ctx->args.num_sgprs_used % num_sgprs != 0) in si_init_shader_args()
728 ac_add_arg(&ctx->args, AC_ARG_SGPR, num_sgprs, AC_ARG_INT, &ctx->cs_image[i]); in si_init_shader_args()
990 if (conf->num_sgprs) { in si_calculate_max_simd_waves()
992 MIN2(max_simd_waves, sscreen->info.num_physical_sgprs_per_simd / conf->num_sgprs); in si_calculate_max_simd_waves()
1022 conf->num_sgprs, conf->num_vgprs, si_get_shader_binary_size(screen, shader), in si_shader_dump_stats_for_shader_db()
1053 conf->num_sgprs, conf->num_vgprs, conf->spilled_sgprs, conf->spilled_vgprs, in si_shader_dump_stats()
1492 if (shader->config.num_sgprs > max_sgprs || shader->config.num_vgprs > max_vgprs) { in si_compile_shader()
1496 shader->config.num_sgprs, shader->config.num_vgprs, max_sgprs, max_vgprs); in si_compile_shader()
1973 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs); in si_fix_resource_usage()
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Dsi_shader_llvm.c534 unsigned num_sgprs, num_vgprs; in si_build_wrapper_function() local
549 num_sgprs = 0; in si_build_wrapper_function()
560 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4; in si_build_wrapper_function()
567 while (gprs < num_sgprs + num_vgprs) { in si_build_wrapper_function()
594 ac_add_arg(&ctx->args, gprs < num_sgprs ? AC_ARG_SGPR : AC_ARG_VGPR, size, arg_type, NULL); in si_build_wrapper_function()
596 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs)); in si_build_wrapper_function()
597 assert(gprs + size <= num_sgprs + num_vgprs && in si_build_wrapper_function()
598 (gprs >= num_sgprs || gprs + size <= num_sgprs)); in si_build_wrapper_function()
Dsi_compute.c99 out_config->num_sgprs = code_object->wavefront_sgpr_count; in code_object_to_config()
157 unsigned num_sgprs = sel->info.base.image_buffers & (1 << i) ? 4 : 8; in si_create_compute_state_async() local
159 if (align(user_sgprs, num_sgprs) + num_sgprs > 16) in si_create_compute_state_async()
162 user_sgprs = align(user_sgprs, num_sgprs); in si_create_compute_state_async()
165 user_sgprs += num_sgprs; in si_create_compute_state_async()
204 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8); in si_create_compute_state_async()
Dsi_state_shaders.c543 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) | in si_shader_ls()
590 (sscreen->info.chip_class <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) in si_shader_hs()
659 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) | in si_shader_es()
937 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_gs()
971 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) | in si_shader_gs()
1527 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_vs()
1739 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_ps()
Dsi_state_draw.cpp1897 unsigned num_sgprs = MIN2(count, num_vbos_in_user_sgprs) * 4; in si_upload_and_prefetch_VB_descriptors() local
1899 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_sgprs); in si_upload_and_prefetch_VB_descriptors()
1900 radeon_emit_array(sctx->vb_descriptor_user_sgprs, num_sgprs); in si_upload_and_prefetch_VB_descriptors()
Dsi_sqtt.c1013 record->shader_data[gl_shader_stage].sgpr_count = shader->config.num_sgprs; in si_sqtt_add_code_object()
Dsi_descriptors.c2182 unsigned num_sgprs = 8; in si_emit_compute_shader_pointers() local
2187 num_sgprs = 4; in si_emit_compute_shader_pointers()
2190 radeon_emit_array(&desc->list[desc_offset], num_sgprs); in si_emit_compute_shader_pointers()
/third_party/mesa3d/src/amd/common/
Dac_binary.c59 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8); in ac_parse_shader_binary_config()
Dac_binary.h38 unsigned num_sgprs; member
Dac_rtld.c531 config->num_sgprs = MAX2(config->num_sgprs, c.num_sgprs); in ac_rtld_read_config()
/third_party/mesa3d/src/amd/vulkan/
Dradv_shader_args.c34 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs) in set_loc() argument
37 ud_info->num_sgprs = num_sgprs; in set_loc()
38 *sgpr_idx += num_sgprs; in set_loc()
42 set_loc_shader(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx, uint8_t num_sgprs) in set_loc_shader() argument
47 set_loc(ud_info, sgpr_idx, num_sgprs); in set_loc_shader()
Dradv_shader.c1337 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3); in radv_postprocess_config() local
1347 config_out->num_sgprs = num_sgprs; in radv_postprocess_config()
1373 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8); in radv_postprocess_config()
1936 S_00B228_SGPRS((bin->num_sgprs - 1) / 8);
2102 if (conf->num_sgprs && chip_class < GFX10) {
2103 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
2223 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
Dradv_shader.h180 uint8_t num_sgprs; member
428 uint8_t num_sgprs; member
Dradv_cmd_buffer.c796 assert(loc->num_sgprs == 1); in radv_emit_userdata_address()
1018 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 2 + loc->num_sgprs); in radv_emit_inline_push_consts()
1020 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs); in radv_emit_inline_push_consts()
1021 radeon_emit_array(cmd_buffer->cs, values, loc->num_sgprs); in radv_emit_inline_push_consts()
2965 assert(loc->num_sgprs == 2); in emit_prolog_inputs()
6979 assert(loc->num_sgprs == 3); in radv_emit_dispatch_packets()
7235 assert(loc->num_sgprs == 3); in radv_CmdTraceRaysKHR()
Dradv_pipeline.c5470 pipeline->graphics.vtx_emit_num = loc->num_sgprs; in radv_pipeline_init_shader_stages_state()
6002 s->value.u64 = shader->config.num_sgprs; in radv_GetPipelineExecutableStatisticsKHR()
/third_party/mesa3d/src/amd/compiler/
Daco_interface.cpp303 prolog_binary->num_sgprs = config.num_sgprs; in aco_compile_vs_prolog()
Daco_validate.cpp310 unsigned num_sgprs = 0; in validate_ir() local
350 if (num_sgprs < 2) in validate_ir()
351 sgpr[num_sgprs++] = op.tempId(); in validate_ir()
359 check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit, in validate_ir()
880 op.physReg() + op.size() > program->config->num_sgprs && in validate_ra()
909 def.physReg() + def.size() > program->config->num_sgprs && in validate_ra()
Daco_optimizer.cpp666 unsigned num_sgprs = 0; in check_vop3_operands() local
675 if (num_sgprs < 2) in check_vop3_operands()
676 sgpr[num_sgprs++] = op.tempId(); in check_vop3_operands()
1810 unsigned num_sgprs = (op[0].type() == RegType::sgpr) + (op[1].type() == RegType::sgpr); in combine_ordering_test() local
1811 if (num_sgprs > (ctx.program->chip_class >= GFX10 ? 2 : 1)) in combine_ordering_test()
1826 if (neg[0] || neg[1] || abs[0] || abs[1] || opsel || num_sgprs > 1) { in combine_ordering_test()
2726 unsigned num_sgprs = !!sgpr_ids[0] + !!sgpr_ids[1]; in apply_sgprs() local
2749 if (!info.is_extract() && num_sgprs && ctx.uses[sgpr_info_id] > 1 && !instr->isVOP3() && in apply_sgprs()
2755 if (new_sgpr && num_sgprs >= max_sgprs) in apply_sgprs()
2783 sgpr_ids[num_sgprs++] = sgpr.id(); in apply_sgprs()
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Daco_instruction_selection.cpp5536 unsigned num_inline_push_consts = loc->sgpr_idx != -1 ? loc->num_sgprs : 0; in visit_load_push_constant()
11987 unsigned num_sgprs = 0; in select_vs_prolog() local
11992 num_sgprs = MAX2(num_sgprs, desc.advance(num_descs * 16u).reg()); in select_vs_prolog()
12144 program->config->num_sgprs = get_sgpr_alloc(program, num_sgprs); in select_vs_prolog()
Daco_register_allocation.cpp2876 program->config->num_sgprs = get_sgpr_alloc(program, ctx.max_used_sgpr + 1); in register_allocation()
/third_party/mesa3d/src/amd/vulkan/layers/
Dradv_sqtt_layer.c885 record->shader_data[i].sgpr_count = shader->config.num_sgprs; in radv_add_code_object()