Home
last modified time | relevance | path

Searched refs:opc (Results 1 – 25 of 144) sorted by relevance

123456

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreInstrFormats.td35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 let Inst{15-11} = opc;
44 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45 : _F3R<opc, outs, ins, asmstr, pattern> {
49 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 let Inst{31-27} = opc{8-4};
53 let Inst{19-16} = opc{3-0};
60 class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
61 list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
65 class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
[all …]
/third_party/wpa_supplicant/wpa_supplicant-2.9_standard/src/crypto/
Dmilenage.c36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f1() argument
44 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f1()
57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i]; in milenage_f1()
67 tmp1[i] ^= opc[i]; in milenage_f1()
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f2345() argument
96 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f2345()
108 tmp1[i] = tmp2[i] ^ opc[i]; in milenage_f2345()
114 tmp3[i] ^= opc[i]; in milenage_f2345()
124 tmp1[(i + 12) % 16] = tmp2[i] ^ opc[i]; in milenage_f2345()
129 ck[i] ^= opc[i]; in milenage_f2345()
[all …]
Dmilenage.h12 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k,
15 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts,
17 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres,
19 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand,
22 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
24 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
/third_party/wpa_supplicant/wpa_supplicant-2.9/src/crypto/
Dmilenage.c36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f1() argument
44 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f1()
57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i]; in milenage_f1()
67 tmp1[i] ^= opc[i]; in milenage_f1()
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f2345() argument
96 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f2345()
108 tmp1[i] = tmp2[i] ^ opc[i]; in milenage_f2345()
114 tmp3[i] ^= opc[i]; in milenage_f2345()
124 tmp1[(i + 12) % 16] = tmp2[i] ^ opc[i]; in milenage_f2345()
129 ck[i] ^= opc[i]; in milenage_f2345()
[all …]
Dmilenage.h12 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k,
15 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts,
17 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres,
19 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand,
22 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
24 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
/third_party/mesa3d/src/freedreno/afuc/
Ddisasm.c102 print_alu_name(afuc_opc opc, uint32_t instr) in print_alu_name() argument
104 if (opc == OPC_ADD) { in print_alu_name()
106 } else if (opc == OPC_ADDHI) { in print_alu_name()
108 } else if (opc == OPC_SUB) { in print_alu_name()
110 } else if (opc == OPC_SUBHI) { in print_alu_name()
112 } else if (opc == OPC_AND) { in print_alu_name()
114 } else if (opc == OPC_OR) { in print_alu_name()
116 } else if (opc == OPC_XOR) { in print_alu_name()
118 } else if (opc == OPC_NOT) { in print_alu_name()
120 } else if (opc == OPC_SHL) { in print_alu_name()
[all …]
Dasm.c146 afuc_opc opc; in emit_instructions() local
164 opc = OPC_NOP; in emit_instructions()
193 opc = tok2alu(ai->tok); in emit_instructions()
198 opc = OPC_ALU; in emit_instructions()
215 opc = OPC_MOVI; in emit_instructions()
224 opc = OPC_MOVI; in emit_instructions()
230 opc = OPC_ALU; in emit_instructions()
244 opc = OPC_CWRITE6; in emit_instructions()
246 opc = OPC_CREAD6; in emit_instructions()
248 opc = OPC_STORE6; in emit_instructions()
[all …]
Dafuc.h211 afuc_get_opc(afuc_instr *ai, afuc_opc *opc, bool *rep) in afuc_get_opc() argument
214 *opc = ai->opc_r >> 1; in afuc_get_opc()
217 *opc = ai->opc_r; in afuc_get_opc()
223 afuc_set_opc(afuc_instr *ai, afuc_opc opc, bool rep) in afuc_set_opc() argument
225 if (opc < 0x30) { in afuc_set_opc()
226 ai->opc_r = opc << 1; in afuc_set_opc()
229 ai->opc_r = opc; in afuc_set_opc()
/third_party/mesa3d/src/freedreno/ir3/
Dinstr-a3xx.h56 #define _OPC(cat, opc) (((cat) << NOPC_BITS) | opc) argument
348 #define opc_cat(opc) ((int)((opc) >> NOPC_BITS)) argument
349 #define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1))) argument
351 const char *disasm_a3xx_instr_name(opc_t opc);
518 is_sat_compatible(opc_t opc) in is_sat_compatible() argument
521 if (opc_cat(opc) != 2 && opc_cat(opc) != 3) in is_sat_compatible()
524 switch (opc) { in is_sat_compatible()
541 is_mad(opc_t opc) in is_mad() argument
543 switch (opc) { in is_mad()
557 is_madsh(opc_t opc) in is_madsh() argument
[all …]
Dir3.c264 if ((instr->opc == OPC_STP || instr->opc == OPC_LDP)) { in ir3_collect_info()
270 if (instr->opc == OPC_STP) in ir3_collect_info()
276 if ((instr->opc == OPC_BARY_F) && (instr->dsts[0]->flags & IR3_REG_EI)) in ir3_collect_info()
282 if (instr->opc == OPC_NOP) { in ir3_collect_info()
286 info->instrs_per_cat[opc_cat(instr->opc)] += 1 + instr->repeat; in ir3_collect_info()
290 if (instr->opc == OPC_MOV) { in ir3_collect_info()
429 instr_create(struct ir3_block *block, opc_t opc, int ndst, int nsrc) in instr_create() argument
432 if (1 <= opc_cat(opc)) in instr_create()
453 ir3_instr_create(struct ir3_block *block, opc_t opc, int ndst, int nsrc) in ir3_instr_create() argument
455 struct ir3_instruction *instr = instr_create(block, opc, ndst, nsrc); in ir3_instr_create()
[all …]
Dir3_validate.c112 if (phi->opc != OPC_META_PHI) in validate_phi_src()
194 } else if (opc_cat(instr->opc) == 1 || opc_cat(instr->opc) == 6) { in validate_instr()
196 } else if (opc_cat(instr->opc) == 0) { in validate_instr()
198 } else if (instr->opc == OPC_META_PARALLEL_COPY) { in validate_instr()
222 switch (opc_cat(instr->opc)) { in validate_instr()
224 if (instr->opc == OPC_MOVMSK || instr->opc == OPC_BALLOT_MACRO) { in validate_instr()
230 } else if (instr->opc == OPC_ANY_MACRO || instr->opc == OPC_ALL_MACRO || in validate_instr()
231 instr->opc == OPC_READ_FIRST_MACRO || in validate_instr()
232 instr->opc == OPC_READ_COND_MACRO) { in validate_instr()
234 } else if (instr->opc == OPC_ELECT_MACRO) { in validate_instr()
[all …]
Dir3_lower_spill.c118 if ((instr->opc == OPC_SPILL_MACRO || instr->opc == OPC_RELOAD_MACRO) && in add_spill_reload_deps()
123 if (instr->opc == OPC_SPILL_MACRO) in add_spill_reload_deps()
131 if ((instr->opc == OPC_SPILL_MACRO || instr->opc == OPC_RELOAD_MACRO) && in add_spill_reload_deps()
136 if (instr->opc == OPC_SPILL_MACRO) in add_spill_reload_deps()
146 if (instr->opc == OPC_SPILL_MACRO) in ir3_lower_spill()
148 else if (instr->opc == OPC_RELOAD_MACRO) in ir3_lower_spill()
155 if (instr->opc == OPC_SPILL_MACRO) in ir3_lower_spill()
156 instr->opc = OPC_STP; in ir3_lower_spill()
157 else if (instr->opc == OPC_RELOAD_MACRO) in ir3_lower_spill()
158 instr->opc = OPC_LDP; in ir3_lower_spill()
Dir3_cf.c31 if (instr->opc != OPC_MOV) in is_safe_conv()
89 opc_t opc = conv_src->opc; in all_uses_safe_conv() local
92 opc_t new_opc = opc; in all_uses_safe_conv()
97 if (!first && opc != new_opc) in all_uses_safe_conv()
100 opc = new_opc; in all_uses_safe_conv()
102 conv_src->opc = opc; in all_uses_safe_conv()
115 assert(use->opc == OPC_MOV); in rewrite_src_uses()
132 if (conv->opc != OPC_MOV) in try_conversion_folding()
Dir3_cp.c178 (is_cat2_float(instr->opc) || is_cat3_float(instr->opc)) ? true : false; in lower_immed()
276 if (!is_mad(instr->opc)) in try_swap_mad_two_srcs()
355 opc_cat(instr->opc) != 0) { in reg_cp()
404 if ((opc_cat(instr->opc) == 3) && (n == 2) && in reg_cp()
418 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type)) in reg_cp()
420 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc)) in reg_cp()
427 if (is_cat2_float(instr->opc) || is_cat3_float(instr->opc)) in reg_cp()
429 if (instr->opc == OPC_MOV && type_float(instr->cat1.src_type)) in reg_cp()
446 debug_assert((opc_cat(instr->opc) == 1) || in reg_cp()
447 (opc_cat(instr->opc) == 2) || in reg_cp()
[all …]
Dir3_legalize.c144 if (is_meta(n) && (n->opc != OPC_META_TEX_PREFETCH)) in legalize_block()
161 if (last_n && (last_n->opc == OPC_PREDT)) { in legalize_block()
226 if ((n->flags & IR3_INSTR_SS) && (opc_cat(n->opc) >= 5)) { in legalize_block()
234 if (list_is_empty(&block->instr_list) && (opc_cat(n->opc) >= 5)) in legalize_block()
239 ctx->type != MESA_SHADER_COMPUTE && n->opc == OPC_SAMGQ) { in legalize_block()
246 samgp->opc = OPC_SAMGP0 + i; in legalize_block()
260 if (n->opc == OPC_META_TEX_PREFETCH) in legalize_block()
262 } else if (n->opc == OPC_RESINFO) { in legalize_block()
270 if ((n->opc == OPC_LDLV) || (n->opc == OPC_LDL) || in legalize_block()
271 (n->opc == OPC_LDLW)) in legalize_block()
[all …]
Dir3_delay.c87 if (consumer->opc == OPC_END || consumer->opc == OPC_CHMASK) in ir3_delayslots()
102 if ((is_mad(consumer->opc) || is_madsh(consumer->opc)) && (n == 2)) { in ir3_delayslots()
119 (is_flow(n) && (n->opc != OPC_JUMP) && (n->opc != OPC_B)); in count_instruction()
147 if (assigner->opc == OPC_META_PHI) in delay_calc_srcn_prera()
250 if (assigner->opc == OPC_MOVMSK) in delay_calc_srcn_postra()
274 if (consumer->opc == OPC_SWZ || consumer->opc == OPC_GAT) in delay_calc_srcn_postra()
280 if (assigner->opc == OPC_SWZ || assigner->opc == OPC_SCT) in delay_calc_srcn_postra()
421 if (instr->opc == OPC_NOP) { in ir3_remove_nops()
Dir3.h234 opc_t opc; member
653 struct ir3_instruction *ir3_instr_create(struct ir3_block *block, opc_t opc,
763 return (opc_cat(instr->opc) == 0); in is_flow()
769 return instr->opc == OPC_KILL || instr->opc == OPC_DEMOTE; in is_kill_or_demote()
775 return instr->opc == OPC_NOP; in is_nop()
803 switch (instr->opc) { in is_same_type_mov()
849 if (instr->opc != OPC_MOV) in is_const_mov()
866 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3); in is_alu()
872 return (opc_cat(instr->opc) == 4); in is_sfu()
878 return (opc_cat(instr->opc) == 5); in is_tex()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DSVEInstrFormats.td258 class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
269 let Inst{18-17} = opc{2-1};
270 let Inst{16} = opc{0};
276 let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
279 multiclass sve_int_ptrue<bits<3> opc, string asm, SDPatternOperator op> {
280 def _B : sve_int_ptrue<0b00, opc, asm, PPR8, nxv16i1, op>;
281 def _H : sve_int_ptrue<0b01, opc, asm, PPR16, nxv8i1, op>;
282 def _S : sve_int_ptrue<0b10, opc, asm, PPR32, nxv4i1, op>;
283 def _D : sve_int_ptrue<0b11, opc, asm, PPR64, nxv2i1, op>;
385 class sve_int_pfalse<bits<6> opc, string asm>
[all …]
DAArch64InstrFormats.td1244 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
1251 let Inst{7-5} = opc;
1442 // case opc of
1449 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
1453 let Inst{24-21} = opc;
1459 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
1460 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1466 class SpecialReturn<bits<4> opc, string asm>
1467 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
1503 class AuthOneOperand<bits<3> opc, bits<1> M, string asm>
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrFormats.td548 string opc, string asm, string cstr,
555 let AsmString = !strconcat(opc, "${p}", asm);
563 string opc, string asm, string cstr,
568 let AsmString = !strconcat(opc, asm);
579 string opc, string asm, string cstr,
589 let AsmString = !strconcat(opc, "${s}${p}", asm);
607 string opc, string asm, list<dag> pattern>
609 opc, asm, "", pattern>;
611 string opc, string asm, list<dag> pattern>
613 opc, asm, "", pattern>;
[all …]
/third_party/mesa3d/src/freedreno/ir2/
Ddisasm-a2xx.c144 #define INSTR(opc, num_srcs) [opc] = {num_srcs, #opc} argument
460 #define INSTR(opc, name, fxn) [opc] = {name, fxn} argument
486 printf("%s", fetch_instructions[fetch->opc].name); in disasm_fetch()
487 fetch_instructions[fetch->opc].fxn(fetch); in disasm_fetch()
500 return (cf->opc == EXEC) || (cf->opc == EXEC_END) || in cf_exec()
501 (cf->opc == COND_EXEC) || (cf->opc == COND_EXEC_END) || in cf_exec()
502 (cf->opc == COND_PRED_EXEC) || (cf->opc == COND_PRED_EXEC_END) || in cf_exec()
503 (cf->opc == COND_EXEC_PRED_CLEAN) || in cf_exec()
504 (cf->opc == COND_EXEC_PRED_CLEAN_END); in cf_exec()
510 return (cf->opc == COND_EXEC) || (cf->opc == COND_EXEC_END) || in cf_cond_exec()
[all …]
/third_party/skia/third_party/externals/spirv-cross/reference/shaders-msl-no-opt/asm/tesc/
Dcopy-memory-control-point.asm.tesc75 …Id, device half (&gl_TessLevelOuter)[3], thread spvUnsafeArray<float4, 4>& opc, constant cb1_struc…
79 opc[as_type<int>(r0.x)].x = cb0_0._m0[0u].x;
80 v_48 = opc[0u];
81 v_49 = opc[1u];
82 v_50 = opc[2u];
93 void fork1(device half &gl_TessLevelInner, thread spvUnsafeArray<float4, 4>& opc, constant cb1_stru…
95 opc[3u].x = cb0_0._m0[0u].x;
96 v_56 = opc[3u];
115 spvUnsafeArray<float4, 4> opc;
119 fork0(0u, spvTessLevel[gl_PrimitiveID].edgeTessellationFactor, opc, cb0_0, v_48, v_49, v_50);
[all …]
/third_party/mesa3d/src/freedreno/isa/
Dencode.c82 if (instr->opc == OPC_B) { in __instruction_case()
99 } else if (instr->opc == OPC_MOV) { in __instruction_case()
114 } else if (instr->opc == OPC_DEMOTE) { in __instruction_case()
117 is_atomic(instr->opc) && (instr->flags & IR3_INSTR_G)) { in __instruction_case()
118 return instr->opc - OPC_ATOMIC_ADD + OPC_ATOMIC_B_ADD; in __instruction_case()
120 if (instr->opc == OPC_RESINFO) { in __instruction_case()
122 } else if (instr->opc == OPC_LDIB) { in __instruction_case()
124 } else if (instr->opc == OPC_STIB) { in __instruction_case()
128 return instr->opc; in __instruction_case()
255 assert(opc_cat(s->instr->opc) == 2); in __multisrc_case()
[all …]
/third_party/libunwind/src/ia64/
DGscript.c243 enum ia64_script_insn_opcode opc; in compile_reg() local
251 opc = IA64_INSN_MOVE; in compile_reg()
262 opc = IA64_INSN_MOVE_STACKED_NAT; in compile_reg()
264 opc = IA64_INSN_MOVE_STACKED; in compile_reg()
272 opc = IA64_INSN_MOVE_NAT; in compile_reg()
278 opc = IA64_INSN_MOVE_SCRATCH_NAT; in compile_reg()
280 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg()
299 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg()
309 opc = IA64_INSN_MOVE_NO_NAT; in compile_reg()
313 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg()
[all …]
/third_party/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_disasm.c41 uint32_t opc : 6; member
458 #define OPC(opc) [INST_OPCODE_##opc] = {#opc, print_opc_default} argument
459 #define OPC_MOV(opc) [INST_OPCODE_##opc] = {#opc, print_opc_mov} argument
460 #define OPC_TEX(opc) [INST_OPCODE_##opc] = {#opc, print_opc_tex} argument
461 #define OPC_IMM(opc) [INST_OPCODE_##opc] = {#opc, print_opc_imm} argument
530 const unsigned opc = instr->opc | (instr->opcode_bit6 << 6); in print_instr() local
531 const char *name = opcs[opc].name; in print_instr()
609 opcs[opc].print(&operands); in print_instr()
611 printf("unknown (%d)", instr->opc); in print_instr()

123456