| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_assembler.cpp | 69 if (instr->operands[3 + i].physReg() != instr->operands[3].physReg().advance(i * 4)) in get_mimg_nsa_dwords()
114 encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 16 : 0; in emit_instruction()
115 encoding |= instr->operands.size() >= 2 ? instr->operands[1].physReg() << 8 : 0; in emit_instruction()
116 encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0; in emit_instruction()
139 encoding |= !instr->definitions.empty() && !(instr->definitions[0].physReg() == scc) in emit_instruction()
140 ? instr->definitions[0].physReg() << 16 in emit_instruction()
141 : !instr->operands.empty() && instr->operands[0].physReg() <= 127 in emit_instruction()
142 ? instr->operands[0].physReg() << 16 in emit_instruction()
154 encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 16 : 0; in emit_instruction()
156 encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0; in emit_instruction()
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| D | aco_lower_to_hw_instr.cpp | 509 vcndmask_identity[i], Operand(PhysReg{src.physReg() + i}, v1), in emit_reduction()
588 bld.readlane(Definition(PhysReg{dst.physReg() + i}, s1), Operand(PhysReg{tmp + i}, v1), in emit_reduction()
591 emit_op(ctx, tmp, dst.physReg(), tmp, vtmp, reduce_op, src.size()); in emit_reduction()
625 bld.readlane(Definition(PhysReg{dst.physReg() + i}, s1), Operand(PhysReg{tmp + i}, v1), in emit_reduction()
628 emit_op(ctx, tmp, dst.physReg(), tmp, vtmp, reduce_op, src.size()); in emit_reduction()
723 identity[i].physReg() == PhysReg{sitmp + i}); in emit_reduction()
816 emit_op(ctx, dst.physReg(), tmp, vtmp, PhysReg{0}, reduce_op, src.size()); in emit_reduction()
829 bld.readlane(Definition(PhysReg{dst.physReg() + k}, s1), Operand(PhysReg{tmp + k}, v1), in emit_reduction()
832 } else if (dst.physReg() != tmp) { in emit_reduction()
834 bld.vop1(aco_opcode::v_mov_b32, Definition(PhysReg{dst.physReg() + k}, v1), in emit_reduction()
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| D | aco_optimizer_postRA.cpp | 91 assert(def.regClass().type() != RegType::sgpr || def.physReg().reg() <= 255); in save_reg_writes()
92 assert(def.regClass().type() != RegType::vgpr || def.physReg().reg() >= 256); in save_reg_writes()
95 unsigned r = def.physReg().reg(); in save_reg_writes()
109 last_writer_idx(pr_opt_ctx& ctx, PhysReg physReg, RegClass rc) in last_writer_idx() argument
112 assert(physReg.reg() < max_reg_cnt); in last_writer_idx()
113 Idx instr_idx = ctx.instr_idx_by_regs[ctx.current_block->index][physReg.reg()]; in last_writer_idx()
115 unsigned r = physReg.reg(); in last_writer_idx()
130 assert(op.physReg().reg() < max_reg_cnt); in last_writer_idx()
131 Idx instr_idx = ctx.instr_idx_by_regs[ctx.current_block->index][op.physReg().reg()]; in last_writer_idx()
135 instr_idx = last_writer_idx(ctx, op.physReg(), op.regClass()); in last_writer_idx()
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| D | aco_insert_NOPs.cpp | 214 if (regs_intersect(reg, mask_size, def.physReg(), def.size())) { in handle_raw_hazard_instr()
215 unsigned start = def.physReg() > reg ? def.physReg() - reg : 0; in handle_raw_hazard_instr()
276 state, state.block, min_states, op.physReg(), u_bit_consecutive(0, op.size()), false); in handle_raw_hazard()
337 test_bitset_range(ctx.smem_clause_write, op.physReg(), op.size())) { in handle_smem_clause_hazards()
344 if (!*NOPs && test_bitset_range(ctx.smem_clause_read_write, def.physReg(), def.size())) in handle_smem_clause_hazards()
400 if (op.physReg() == vccz) in handle_instruction_gfx6()
402 if (op.physReg() == execz) in handle_instruction_gfx6()
414 NOPs = MAX2(NOPs, ctx.vmem_store_then_wr_data[(def.physReg() & 0xff) + i]); in handle_instruction_gfx6()
493 set_bitset_range(ctx.smem_clause_read_write, op.physReg(), op.size()); in handle_instruction_gfx6()
498 set_bitset_range(ctx.smem_clause_read_write, def.physReg(), def.size()); in handle_instruction_gfx6()
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| D | aco_ssa_elimination.cpp | 66 if (phi->operands[i].physReg() == phi->definitions[0].physReg()) in collect_phi_info()
152 if (ignore_exec_writes && instr->definitions[i].physReg() == exec) in is_empty_block()
154 if (instr->definitions[i].physReg() != instr->operands[i].physReg()) in is_empty_block()
160 if (ignore_exec_writes && instr->definitions[0].physReg() == exec) in is_empty_block()
292 if (def.physReg() == exec || def.physReg() == exec_hi) in instr_writes_exec()
312 copy_to_exec |= successor_phi_info.def.physReg() == exec; in eliminate_useless_exec_writes_in_block()
313 copy_from_exec |= successor_phi_info.op.physReg() == exec; in eliminate_useless_exec_writes_in_block()
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| D | aco_register_allocation.cpp | 58 reg = def.physReg(); in set()
305 fill_subdword(op.physReg(), op.bytes(), op.tempId()); in fill()
307 fill(op.physReg(), op.size(), op.tempId()); in fill()
310 void clear(Operand op) { clear(op.physReg(), op.regClass()); } in clear()
315 fill_subdword(def.physReg(), def.bytes(), def.tempId()); in fill()
317 fill(def.physReg(), def.size(), def.tempId()); in fill()
320 void clear(Definition def) { clear(def.physReg(), def.regClass()); } in clear()
745 def.setFixed(it->second.physReg()); in update_renames()
747 ctx.assignments[def.tempId()].reg = def.physReg(); in update_renames()
761 other.second.setFixed(it->second.physReg()); in update_renames()
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| D | aco_validate.cpp | 163 check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) || in validate_ir()
195 check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc, in validate_ir()
199 check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc, in validate_ir()
475 instr->definitions[1].physReg() == scc, in validate_ir()
586 check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0, in validate_ir()
714 unsigned byte = op.physReg().byte(); in validate_subdword_operand()
768 unsigned byte = def.physReg().byte(); in validate_subdword_definition()
873 if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg()) in validate_ra()
878 op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) || in validate_ra()
880 op.physReg() + op.size() > program->config->num_sgprs && in validate_ra()
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| D | aco_live_var_analysis.cpp | 121 if ((definition.isFixed() || definition.hasHint()) && definition.physReg() == vcc) in process_live_temps_per_block()
150 if (operand.isFixed() && operand.physReg() == vcc) in process_live_temps_per_block()
187 assert(insn->definitions[0].isFixed() && insn->definitions[0].physReg() == exec); in process_live_temps_per_block()
192 if ((definition.isFixed() || definition.hasHint()) && definition.physReg() == vcc) in process_live_temps_per_block()
243 if (operand.isFixed() && operand.physReg() == vcc) in process_live_temps_per_block()
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| D | aco_opt_value_numbering.cpp | 140 if (a->operands[i].physReg() != b->operands[i].physReg()) in operator ()()
142 if (a->operands[i].physReg() == exec && a->pass_flags != b->pass_flags) in operator ()()
156 if (a->definitions[i].physReg() != b->definitions[i].physReg()) in operator ()()
158 if (a->definitions[i].physReg() == exec) in operator ()()
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| D | aco_insert_waitcnt.cpp | 254 PhysReg reg{op.physReg() + j}; in check_instr()
266 PhysReg reg{def.physReg() + j}; in check_instr()
294 instr->definitions[0].physReg() == sgpr_null) { in parse_wait_instr()
599 insert_wait_entry(ctx, op.physReg(), op.regClass(), event, false, has_sampler); in insert_wait_entry()
605 insert_wait_entry(ctx, def.physReg(), def.regClass(), event, true, has_sampler); in insert_wait_entry()
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| D | aco_print_ir.cpp | 167 print_constant(operand->physReg().reg(), output); in aco_print_operand()
185 print_physReg(operand->physReg(), operand->bytes(), output, flags); in aco_print_operand()
206 print_physReg(definition->physReg(), definition->bytes(), output, flags); in print_definition()
618 offset += instr->definitions[0].physReg().byte(); in print_instr_format_specific()
632 offset += instr->operands[i].physReg().byte(); in print_instr_format_specific()
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| D | aco_statistics.cpp | 314 deps_available = MAX2(deps_available, reg_available[op.physReg().reg() + i]); in get_dependency_cost()
399 int32_t* available = ®_available[def.physReg().reg()]; in add()
481 blocks[0].reg_available[def.physReg().reg() + i] = vs_input_latency; in collect_preasm_stats()
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| D | aco_ir.h | 750 constexpr PhysReg physReg() const noexcept { return reg_; } in physReg() function
839 if (isFixed() && other.isFixed() && physReg() != other.physReg())
844 return other.isConstant() && other.physReg() == physReg();
925 constexpr PhysReg physReg() const noexcept { return reg_; } in physReg() function
1015 if (op.isFixed() && op.physReg() == exec) in reads_exec()
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| D | aco_ir.cpp | 309 instr->definitions.back().physReg() != vcc) in can_use_DPP()
312 if (!pre_ra && instr->operands.size() >= 3 && instr->operands[2].physReg() != vcc) in can_use_DPP()
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| D | aco_lower_to_cssa.cpp | 112 assert(op.isFixed() && op.physReg() == exec); in collect_parallelcopies()
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| D | aco_spill.cpp | 198 if (op.isFixed() && op.physReg() == exec) in next_uses_per_block()
408 if (op.isFixed() && op.physReg() == exec) in update_local_next_uses()
1027 assert(phi->definitions[0].isFixed() && phi->definitions[0].physReg() == exec); in add_coupling_code()
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| D | aco_scheduler.cpp | 565 if (def.isFixed() && def.physReg() == exec) in perform_hazard_query()
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| D | aco_optimizer.cpp | 785 return op.isFixed() && op.physReg() == exec; in fixed_to_exec()
2056 if (!instr->operands[0].isFixed() || instr->operands[0].physReg() != exec) in combine_inverse_comparison()
3610 pred_instr->definitions[1].physReg() == scc); in to_uniform_bool_instr()
3768 instr->operands[0].isFixed() && instr->operands[0].physReg() == scc) { in select_instruction()
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| D | aco_instruction_selection.cpp | 139 assert(mask.isUndefined() || mask.isTemp() || (mask.isFixed() && mask.physReg() == exec)); in emit_mbcnt()
156 } else if (mask.physReg() == exec) { in emit_mbcnt()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | VirtRegMap.cpp | 83 void VirtRegMap::assignVirt2Phys(Register virtReg, MCPhysReg physReg) { in assignVirt2Phys() argument
84 assert(virtReg.isVirtual() && Register::isPhysicalRegister(physReg)); in assignVirt2Phys()
88 assert(!getRegInfo().isReserved(physReg) && in assignVirt2Phys()
90 Virt2PhysMap[virtReg.id()] = physReg; in assignVirt2Phys()
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| D | InterferenceCache.cpp | 104 void InterferenceCache::Entry::reset(unsigned physReg, in reset() argument
111 PhysReg = physReg; in reset()
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| D | InterferenceCache.h | 123 void reset(unsigned physReg,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | VirtRegMap.h | 109 void assignVirt2Phys(Register virtReg, MCPhysReg physReg);
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