Searched refs:reg_idx (Results 1 – 10 of 10) sorted by relevance
| /third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| D | ir2.c | 105 insert(struct ir2_context *ctx, unsigned block_idx, unsigned reg_idx, in insert() argument
126 unsigned mr = ~(s->reg_state[reg_idx / 8] >> reg_idx % 8 * 4 & 0xf); in insert()
143 s->reg_state[reg_idx / 8] |= 1 << (*comp + reg_idx % 8 * 4); in insert()
|
| D | ir2_nir.c | 531 unsigned reg_idx = instr->reg - ctx->reg; /* XXX */ in load_input() local
533 instr->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG); in load_input()
717 unsigned reg_idx; in emit_tex() local
725 reg_idx = instr->reg - ctx->reg; /* hacky */ in emit_tex()
728 rcp->src[0] = ir2_src(reg_idx, IR2_SWIZZLE_Z, IR2_SRC_REG); in emit_tex()
732 coord_xy->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG); in emit_tex()
736 src_coord = ir2_src(reg_idx, 0, IR2_SRC_REG); in emit_tex()
|
| /third_party/mesa3d/src/gallium/drivers/svga/ |
| D | svga_pipe_streamout.c | 187 unsigned reg_idx = info->output[i].register_index; in svga_create_stream_output() local
190 shader->info.output_semantic_name[reg_idx]; in svga_create_stream_output()
198 i, reg_idx, buf_idx, info->output[i].stream); in svga_create_stream_output()
257 shader->info.output_semantic_index[reg_idx]; in svga_create_stream_output()
260 decls[numDecls].registerIndex = reg_idx; in svga_create_stream_output()
|
| /third_party/ffmpeg/libavcodec/ |
| D | nvenc.c | 1821 int reg_idx = nvenc_register_frame(avctx, frame); in nvenc_upload_frame() local
1822 if (reg_idx < 0) { in nvenc_upload_frame()
1824 return reg_idx; in nvenc_upload_frame()
1831 if (!ctx->registered_frames[reg_idx].mapped) { in nvenc_upload_frame()
1832 ctx->registered_frames[reg_idx].in_map.version = NV_ENC_MAP_INPUT_RESOURCE_VER; in nvenc_upload_frame()
1833 …ctx->registered_frames[reg_idx].in_map.registeredResource = ctx->registered_frames[reg_idx].regptr; in nvenc_upload_frame()
1834 …v_status = p_nvenc->nvEncMapInputResource(ctx->nvencoder, &ctx->registered_frames[reg_idx].in_map); in nvenc_upload_frame()
1841 ctx->registered_frames[reg_idx].mapped += 1; in nvenc_upload_frame()
1843 nvenc_frame->reg_idx = reg_idx; in nvenc_upload_frame()
1844 … nvenc_frame->input_surface = ctx->registered_frames[reg_idx].in_map.mappedResource; in nvenc_upload_frame()
[all …]
|
| D | nvenc.h | 77 int reg_idx; member
|
| /third_party/mesa3d/src/gallium/drivers/lima/ir/gp/ |
| D | regalloc.c | 366 int reg_idx; in assign_regs() local
367 BITSET_FOREACH_SET(reg_idx, block->live_out, ctx->comp->cur_reg) { in assign_regs()
368 if (BITSET_TEST(block->def_out, reg_idx)) { in assign_regs()
369 block->live_out_phys |= (1ull << ctx->registers[reg_idx].assigned_color); in assign_regs()
|
| /third_party/freetype/src/psaux/ |
| D | cffdecode.c | 1917 FT_Int reg_idx = (FT_Int)args[0]; in cff_decoder_parse_charstrings() local
1927 if ( reg_idx >= 0 && reg_idx <= 2 && in cff_decoder_parse_charstrings()
|
| /third_party/flutter/skia/third_party/externals/freetype/src/psaux/ |
| D | cffdecode.c | 1915 FT_Int reg_idx = (FT_Int)args[0]; in cff_decoder_parse_charstrings() local
1925 if ( reg_idx >= 0 && reg_idx <= 2 && in cff_decoder_parse_charstrings()
|
| /third_party/skia/third_party/externals/freetype/src/psaux/ |
| D | cffdecode.c | 1917 FT_UInt reg_idx = (FT_UInt)args[0]; in cff_decoder_parse_charstrings() local
1927 if ( reg_idx <= 2 && in cff_decoder_parse_charstrings()
|
| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 7503 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset, int eg_buffer_b… in r600_do_buffer_txq() argument
7507 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset; in r600_do_buffer_txq()
7508 …int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_… in r600_do_buffer_txq()
|