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Searched refs:reg_offset (Results 1 – 25 of 26) sorted by relevance

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/third_party/mesa3d/src/intel/compiler/
Dbrw_ir_fs.h181 reg_offset(const fs_reg &r) in reg_offset() function
224 !(reg_offset(r) + dr <= reg_offset(s) || in regions_overlap()
225 reg_offset(s) + ds <= reg_offset(r)); in regions_overlap()
238 reg_offset(r) >= reg_offset(s) && in region_contained_in()
239 reg_offset(r) + dr <= reg_offset(s) + ds; in region_contained_in()
448 return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + in regs_written()
467 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + in regs_read()
Dbrw_ir_vec4.h232 reg_offset(const backend_reg &r) in reg_offset() function
264 !(reg_offset(r) + dr <= reg_offset(s) || in regions_overlap()
265 reg_offset(s) + ds <= reg_offset(r)); in regions_overlap()
421 return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + inst->size_written, in regs_written()
436 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + inst->size_read(i), in regs_read()
Dbrw_fs_lower_regioning.cpp114 if (reg_offset(inst->src[i]) % REG_SIZE != in required_dst_byte_offset()
115 reg_offset(inst->dst) % REG_SIZE) in required_dst_byte_offset()
119 return reg_offset(inst->dst) % REG_SIZE; in required_dst_byte_offset()
146 reg_offset(inst->src[i]) % REG_SIZE > 0 && in has_invalid_src_region()
154 const unsigned dst_byte_offset = reg_offset(inst->dst) % REG_SIZE; in has_invalid_src_region()
155 const unsigned src_byte_offset = reg_offset(inst->src[i]) % REG_SIZE; in has_invalid_src_region()
175 const unsigned dst_byte_offset = reg_offset(inst->dst) % REG_SIZE; in has_invalid_dst_region()
Dbrw_vec4_visitor.cpp1327 src_reg *reladdr, int reg_offset) in get_scratch_offset() argument
1349 brw_imm_d(reg_offset))); in get_scratch_offset()
1356 brw_imm_d(reg_offset * message_header_scale))); in get_scratch_offset()
1360 return brw_imm_d(reg_offset * message_header_scale); in get_scratch_offset()
1376 int reg_offset = base_offset + orig_src.offset / REG_SIZE; in emit_scratch_read() local
1378 reg_offset); in emit_scratch_read()
1386 index = get_scratch_offset(block, inst, orig_src.reladdr, reg_offset + 1); in emit_scratch_read()
1405 int reg_offset = base_offset + inst->dst.offset / REG_SIZE; in emit_scratch_write() local
1407 reg_offset); in emit_scratch_write()
1463 reg_offset + 1); in emit_scratch_write()
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Dbrw_vec4.h288 src_reg *reladdr, int reg_offset);
Dbrw_fs_copy_propagation.cpp570 (reg_offset(inst->dst) % REG_SIZE) != (reg_offset(entry->src) % REG_SIZE)) in try_copy_propagate()
Dbrw_fs_bank_conflicts.cpp501 return reg_offset(r) / REG_SIZE; in reg_of()
Dbrw_fs_scoreboard.cpp715 reg_offset(r) / REG_SIZE); in dep()
Dbrw_fs.cpp2226 unsigned reg_offset = 0; in split_virtual_grfs() local
2227 while (reg_offset < inst->size_written / REG_SIZE) { in split_virtual_grfs()
2228 reg = vgrf_to_reg[inst->dst.nr] + reg_offset; in split_virtual_grfs()
2230 reg_offset += alloc.sizes[new_virtual_grf[reg]]; in split_virtual_grfs()
3228 const int rel_offset = reg_offset(s) - reg_offset(r); in mask_relative_to()
3372 const unsigned rel_offset = reg_offset(scan_inst->dst) - in compute_to_mrf()
3373 reg_offset(inst->src[0]); in compute_to_mrf()
/third_party/mesa3d/src/amd/common/
Dac_shadowed_regs.c2935 unsigned reg_offset = R_02835C_PA_SC_TILE_STEERING_OVERRIDE; in ac_emulate_clear_state() local
2939 gfx103_emulate_clear_state(cs, 1, &reg_offset, &reg_value, set_context_reg_seq_array); in ac_emulate_clear_state()
2941 gfx10_emulate_clear_state(cs, 1, &reg_offset, &reg_value, set_context_reg_seq_array); in ac_emulate_clear_state()
2953 unsigned reg_offset, unsigned count) in ac_check_shadowed_regs() argument
2965 unsigned end_reg_offset = reg_offset + count * 4; in ac_check_shadowed_regs()
2969 if (MAX2(ranges[i].offset, reg_offset) < MIN2(end_range_offset, end_reg_offset)) { in ac_check_shadowed_regs()
2978 if (reg_offset == R_00B858_COMPUTE_DESTINATION_EN_SE0 || in ac_check_shadowed_regs()
2979 reg_offset == R_00B864_COMPUTE_DESTINATION_EN_SE2) in ac_check_shadowed_regs()
2985 printf("%s .. %s\n", ac_get_register_name(chip_class, reg_offset), in ac_check_shadowed_regs()
2986 ac_get_register_name(chip_class, reg_offset + (count - 1) * 4)); in ac_check_shadowed_regs()
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Dac_shadowed_regs.h63 unsigned reg_offset, unsigned count);
Dac_debug.c237 static void ac_parse_set_reg_packet(FILE *f, unsigned count, unsigned reg_offset, in ac_parse_set_reg_packet() argument
241 unsigned reg = ((reg_dw & 0xFFFF) << 2) + reg_offset; in ac_parse_set_reg_packet()
/third_party/ffmpeg/libavcodec/
Datrac3plusdsp.c131 int invert_phase, int reg_offset, float *out) in waves_synth() argument
145 pos = DEQUANT_PHASE(wave_param->phase_index) - (reg_offset ^ 128) * inc & 2047; in waves_synth()
160 pos = (envelope->start_pos << 2) - reg_offset; in waves_synth()
175 pos = (envelope->stop_pos + 1 << 2) - reg_offset; in waves_synth()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h37 #define SI_CHECK_SHADOWED_REGS(reg_offset, count) ac_check_shadowed_regs(GFX10, CHIP_NAVI14, reg_of…
39 #define SI_CHECK_SHADOWED_REGS(reg_offset, count) argument
/third_party/mesa3d/src/intel/tools/
Daub_read.h51 void (*reg_write)(void *user_data, uint32_t reg_offset, uint32_t reg_value);
Daubinator_viewer.cpp108 handle_reg_write(void *user_data, uint32_t reg_offset, uint32_t reg_value) in handle_reg_write() argument
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_winsys.c124 radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws, unsigned reg_offset, in radv_amdgpu_winsys_read_registers() argument
129 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, 0xffffffff, 0, out) == 0; in radv_amdgpu_winsys_read_registers()
/third_party/mesa3d/src/gallium/drivers/r600/
Deg_debug.c134 unsigned reg_offset) in ac_parse_set_reg_packet() argument
136 unsigned reg = (ib[1] << 2) + reg_offset; in ac_parse_set_reg_packet()
/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_winsys.c280 unsigned reg_offset, in amdgpu_read_registers() argument
285 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, in amdgpu_read_registers()
/third_party/mesa3d/src/panfrost/midgard/
Dmidgard_ra.c45 offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcshift, unsigned dstshift, unsign… in offset_swizzle() argument
49 signed reg_comp = reg_offset >> srcshift; in offset_swizzle()
54 assert(reg_comp << srcshift == reg_offset); in offset_swizzle()
/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/
Dregalloc.c397 unsigned reg_offset = ctx->alloc_start++; in find_free_value_reg() local
405 unsigned cur_reg = (reg_base + reg_offset) % (GPIR_PHYSICAL_REG_NUM + GPIR_VALUE_REG_NUM); in find_free_value_reg()
/third_party/mesa3d/src/amd/vulkan/
Dradv_radeon_winsys.h221 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers,
/third_party/mesa3d/src/gallium/drivers/r600/sb/
Dsb_ir.h600 int reg_offset = select.sel() - array->base_gpr.sel(); in get_final_gpr() local
602 reg_offset += rel->get_const_value().i; in get_final_gpr()
603 return array->gpr + (reg_offset << 2); in get_final_gpr()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_winsys.c764 unsigned reg_offset, in radeon_read_registers() argument
771 uint32_t reg = reg_offset + i*4; in radeon_read_registers()
/third_party/mesa3d/src/gallium/drivers/radeon/
Dradeon_winsys.h697 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers,

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