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Searched refs:shadowed_regs (Results 1 – 8 of 8) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_cp_reg_shadowing.c136 si_build_load_reg(sctx->screen, pm4, i, sctx->shadowed_regs); in si_create_shadowing_ib_preamble()
154 sctx->shadowed_regs = in si_init_cp_reg_shadowing()
160 if (!sctx->shadowed_regs) in si_init_cp_reg_shadowing()
164 si_init_cs_preamble_state(sctx, sctx->shadowed_regs != NULL); in si_init_cp_reg_shadowing()
166 if (sctx->shadowed_regs) { in si_init_cp_reg_shadowing()
168 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, &sctx->shadowed_regs->b.b, in si_init_cp_reg_shadowing()
169 0, sctx->shadowed_regs->bo_size, 0, SI_OP_SYNC_AFTER, in si_init_cp_reg_shadowing()
177 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->shadowed_regs, in si_init_cp_reg_shadowing()
Dsi_gfx_cs.c392 if (ctx->shadowed_regs) { in si_begin_new_gfx_cs()
393 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->shadowed_regs, in si_begin_new_gfx_cs()
400 if (first_cs || !ctx->shadowed_regs) { in si_begin_new_gfx_cs()
445 if (has_clear_state || ctx->shadowed_regs) { in si_begin_new_gfx_cs()
463 if (first_cs || !ctx->shadowed_regs) { in si_begin_new_gfx_cs()
Dsi_pm4.c135 if (!first_cs && sctx->shadowed_regs) { in si_pm4_reset_emitted()
Dsi_state_draw.cpp1349 if (index_size != sctx->last_index_size || sctx->shadowed_regs) { in si_emit_draw_packets()
1466 if (sctx->shadowed_regs || in si_emit_draw_packets()
Dsi_state_shaders.c3533 assert(!sctx->shadowed_regs); in si_cs_preamble_add_vgt_flush()
3648 if (sctx->shadowed_regs) { in si_update_gs_ring_buffers()
3914 if (sctx->shadowed_regs) { in si_init_tess_factor_ring()
Dsi_pipe.h919 struct si_resource *shadowed_regs; member
Dsi_pipe.c331 si_resource_reference(&sctx->shadowed_regs, NULL); in si_destroy_context()
Dsi_descriptors.c2087 } else if (sctx->chip_class == GFX9 && sctx->shadowed_regs) { in si_emit_global_shader_pointers()