/third_party/gstreamer/gstplugins_base/gst-libs/gst/fft/ |
D | _kiss_fft_guts_s32.h | 73 # define smul(a,b) ( (SAMPPROD)(a)*(b) ) macro 76 # define S_MUL(a,b) sround( smul(a,b) ) 79 do{ (m).r = sround( smul((a).r,(b).r) - smul((a).i,(b).i) ); \ 80 (m).i = sround( smul((a).r,(b).i) + smul((a).i,(b).r) ); }while(0) 83 (x) = sround( smul( x, SAMP_MAX/k ) ) 90 do{ (c).r = sround( smul( (c).r , s ) ) ;\ 91 (c).i = sround( smul( (c).i , s ) ) ; }while(0)
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D | _kiss_fft_guts_f64.h | 73 # define smul(a,b) ( (SAMPPROD)(a)*(b) ) macro 76 # define S_MUL(a,b) sround( smul(a,b) ) 79 do{ (m).r = sround( smul((a).r,(b).r) - smul((a).i,(b).i) ); \ 80 (m).i = sround( smul((a).r,(b).i) + smul((a).i,(b).r) ); }while(0) 83 (x) = sround( smul( x, SAMP_MAX/k ) ) 90 do{ (c).r = sround( smul( (c).r , s ) ) ;\ 91 (c).i = sround( smul( (c).i , s ) ) ; }while(0)
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D | _kiss_fft_guts_s16.h | 73 # define smul(a,b) ( (SAMPPROD)(a)*(b) ) macro 76 # define S_MUL(a,b) sround( smul(a,b) ) 79 do{ (m).r = sround( smul((a).r,(b).r) - smul((a).i,(b).i) ); \ 80 (m).i = sround( smul((a).r,(b).i) + smul((a).i,(b).r) ); }while(0) 83 (x) = sround( smul( x, SAMP_MAX/k ) ) 90 do{ (c).r = sround( smul( (c).r , s ) ) ;\ 91 (c).i = sround( smul( (c).i , s ) ) ; }while(0)
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D | _kiss_fft_guts_f32.h | 73 # define smul(a,b) ( (SAMPPROD)(a)*(b) ) macro 76 # define S_MUL(a,b) sround( smul(a,b) ) 79 do{ (m).r = sround( smul((a).r,(b).r) - smul((a).i,(b).i) ); \ 80 (m).i = sround( smul((a).r,(b).i) + smul((a).i,(b).r) ); }while(0) 83 (x) = sround( smul( x, SAMP_MAX/k ) ) 90 do{ (c).r = sround( smul( (c).r , s ) ) ;\ 91 (c).i = sround( smul( (c).i , s ) ) ; }while(0)
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/third_party/mesa3d/src/panfrost/midgard/ |
D | midgard_schedule.c | 1096 midgard_instruction **smul, in mir_schedule_zs_write() argument 1108 midgard_instruction **units[] = { smul, vadd, vlut }; in mir_schedule_zs_write() 1177 midgard_instruction *smul = NULL; in mir_schedule_alu() local 1191 smul = cond; in mir_schedule_alu() 1256 …zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, fals… in mir_schedule_alu() 1259 …zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, true… in mir_schedule_alu() 1261 mir_choose_alu(&smul, instructions, liveness, worklist, len, &predicate, UNIT_SMUL); in mir_schedule_alu() 1276 mir_update_worklist(worklist, len, instructions, smul); in mir_schedule_alu() 1279 bool smul_csel = smul && OP_IS_CSEL(smul->op); in mir_schedule_alu() 1282 midgard_instruction *ins = vadd_csel ? vadd : smul; in mir_schedule_alu() [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
D | IntrinsicEnums.inc | 243 smul_fix, // llvm.smul.fix 244 smul_fix_sat, // llvm.smul.fix.sat 245 smul_with_overflow, // llvm.smul.with.overflow
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D | IntrinsicImpl.inc | 271 "llvm.smul.fix", 272 "llvm.smul.fix.sat", 273 "llvm.smul.with.overflow", 10404 49, // llvm.smul.fix 10405 49, // llvm.smul.fix.sat 10406 4, // llvm.smul.with.overflow
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/third_party/alsa-lib/src/pcm/ |
D | pcm_route.c | 936 unsigned int sused, dused, smul, dmul; in route_load_ttable() local 940 smul = tt_ssize; in route_load_ttable() 945 smul = 1; in route_load_ttable() 961 v = ttable[src_channel * smul + dst_channel * dmul]; in route_load_ttable()
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/third_party/mesa3d/src/compiler/spirv/ |
D | vtn_alu.c | 541 nir_ssa_def *smul = nir_imul_2x32_64(&b->nb, src[0], src[1]); in vtn_handle_alu() local 542 dest->elems[0]->def = nir_unpack_64_2x32_split_x(&b->nb, smul); in vtn_handle_alu() 543 dest->elems[1]->def = nir_unpack_64_2x32_split_y(&b->nb, smul); in vtn_handle_alu()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
D | SparcInstrInfo.td | 743 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>;
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/third_party/libxml2/result/ |
D | rdf2.rdr | 829 /usr/share/ncurses4/terminfo/h/h19-smul
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D | rdf2.rde | 829 /usr/share/ncurses4/terminfo/h/h19-smul
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMInstrInfo.td | 4382 defm SMUL : AI_smul<"smul">; 5858 // smul* and smla*
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/third_party/mesa3d/docs/relnotes/ |
D | 19.3.0.rst | 368 - pan/midgard: Schedule to smul/sadd
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D | 19.1.0.rst | 430 - panfrost/midgard: Promote smul to vmul
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D | 20.2.0.rst | 658 - pan/mdg: Defer smul, vlut until after writeout moves
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/ |
D | Intrinsics.gen | 142 smul_with_overflow, // llvm.smul.with.overflow 6200 "llvm.smul.with.overflow", 14140 1, // llvm.smul.with.overflow
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
D | Intrinsics.gen | 142 smul_with_overflow, // llvm.smul.with.overflow 6200 "llvm.smul.with.overflow", 14140 1, // llvm.smul.with.overflow
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
D | Intrinsics.gen | 142 smul_with_overflow, // llvm.smul.with.overflow 6200 "llvm.smul.with.overflow", 14140 1, // llvm.smul.with.overflow
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
D | Intrinsics.gen | 142 smul_with_overflow, // llvm.smul.with.overflow 6200 "llvm.smul.with.overflow", 14140 1, // llvm.smul.with.overflow
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
D | Intrinsics.gen | 134 smul_with_overflow, // llvm.smul.with.overflow 6158 "llvm.smul.with.overflow", 14043 1, // llvm.smul.with.overflow
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