| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | BUFInstructions.td | 132 bits<8> soffset;
143 (ins SReg_128:$srsrc, SCSrc_b32:$soffset,
145 (ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
150 SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, GLC:$glc,
153 SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, GLC:$glc,
171 !if(!eq(addrKind, BUFAddrKind.Offset), "off, $srsrc, $format, $soffset",
173 "$vaddr, $srsrc, $format, $soffset offen",
175 "$vaddr, $srsrc, $format, $soffset idxen",
177 "$vaddr, $srsrc, $format, $soffset idxen offen",
179 "$vaddr, $srsrc, $format, $soffset addr64",
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| D | SIRegisterInfo.cpp | 401 assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() == in resolveFrameIndex()
598 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
1029 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
1059 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
1195 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
1198 TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->setReg(FrameReg); in eliminateFrameIndex()
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| D | SILoadStoreOptimizer.cpp | 535 AddrOpName[NumAddresses++] = AMDGPU::OpName::soffset; in setMI()
1251 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferLoadPair()
1316 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferLoadPair()
1395 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferStorePair()
1555 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferStorePair()
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| D | SIInstrInfo.td | 84 SDTCisVT<4, i32>, // soffset(SGPR)
102 SDTCisVT<4, i32>, // soffset(SGPR)
120 SDTCisVT<4, i32>, // soffset(SGPR)
146 SDTCisVT<4, i32>, // soffset(SGPR)
171 SDTCisVT<5, i32>, // soffset(SGPR)
184 SDTCisVT<4, i32>, // soffset(SGPR)
214 SDTCisVT<6, i32>, // soffset(SGPR)
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| D | SIInstructions.td | 548 SReg_32:$soffset, i32imm:$offset)> {
559 (ins i32imm:$vaddr, SReg_128:$srsrc, SReg_32:$soffset,
588 SReg_32:$soffset, i32imm:$offset)> {
599 (ins i32imm:$vaddr, SReg_128:$srsrc, SReg_32:$soffset,
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| D | GCNHazardRecognizer.cpp | 690 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
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| D | SIFoldOperands.cpp | 615 MachineOperand *SOff = TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset); in foldOperand()
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| D | SIInstrInfo.cpp | 217 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || in areLoadsFromSameBasePtr()
326 const MachineOperand *SOffset = getNamedOperand(LdSt, AMDGPU::OpName::soffset); in getMemOperandWithOffset()
4756 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands()
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| /third_party/mesa3d/src/amd/llvm/ |
| D | ac_llvm_build.h | 257 unsigned num_channels, LLVMValueRef voffset, LLVMValueRef soffset,
264 LLVMValueRef vindex, LLVMValueRef voffset, LLVMValueRef soffset,
274 LLVMValueRef voffset, LLVMValueRef soffset,
278 LLVMValueRef voffset, LLVMValueRef soffset,
283 LLVMValueRef soffset, LLVMValueRef immoffset,
288 LLVMValueRef voffset, LLVMValueRef soffset,
297 LLVMValueRef soffset, unsigned cache_policy,
301 LLVMValueRef vdata, LLVMValueRef voffset, LLVMValueRef soffset,
305 LLVMValueRef voffset, LLVMValueRef soffset, unsigned cache_policy);
309 LLVMValueRef soffset, LLVMValueRef immoffset,
[all …]
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| D | ac_llvm_build.c | 1120 LLVMValueRef voffset, LLVMValueRef soffset, in ac_build_buffer_store_common() argument
1130 args[idx++] = soffset ? soffset : ctx->i32_0; in ac_build_buffer_store_common()
1158 unsigned num_channels, LLVMValueRef voffset, LLVMValueRef soffset, in ac_build_buffer_store_dword() argument
1170 ac_build_buffer_store_dword(ctx, rsrc, v01, 2, voffset, soffset, inst_offset, cache_policy); in ac_build_buffer_store_dword()
1171 ac_build_buffer_store_dword(ctx, rsrc, v[2], 1, voffset, soffset, inst_offset + 8, in ac_build_buffer_store_dword()
1181 LLVMValueRef offset = soffset; in ac_build_buffer_store_dword()
1198 ac_build_raw_tbuffer_store(ctx, rsrc, vdata, voffset, soffset, immoffset, num_channels, dfmt, in ac_build_buffer_store_dword()
1204 LLVMValueRef soffset, unsigned num_channels, in ac_build_buffer_load_common() argument
1215 args[idx++] = soffset ? soffset : ctx->i32_0; in ac_build_buffer_load_common()
1240 LLVMValueRef vindex, LLVMValueRef voffset, LLVMValueRef soffset, in ac_build_buffer_load() argument
[all …]
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader_llvm_gs.c | 50 LLVMValueRef vtx_offset, soffset; in si_llvm_load_input_gs() local
78 soffset = LLVMConstInt(ctx->ac.i32, (param * 4 + swizzle) * 256, 0); in si_llvm_load_input_gs()
80 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->ac.i32_0, vtx_offset, soffset, 0, in si_llvm_load_input_gs()
238 LLVMValueRef soffset = ac_get_arg(&ctx->ac, ctx->args.gs2vs_offset); in si_llvm_emit_vertex() local
283 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring[stream], out_val, 1, voffset, soffset, in si_llvm_emit_vertex()
496 LLVMValueRef soffset = in si_generate_gs_copy_shader() local
501 ac_build_buffer_load(&ctx.ac, ctx.gsvs_ring[0], 1, ctx.ac.i32_0, voffset, soffset, 0, in si_generate_gs_copy_shader()
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| /third_party/flatbuffers/python/flatbuffers/ |
| D | packer.py | 41 soffset = int32 variable
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| D | builder.py | 248 encode.Write(packer.soffset, self.Bytes, objectStart,
261 encode.Write(packer.soffset, self.Bytes, self.Head(),
744 encode.Write(packer.soffset, self.Bytes, self.Head(), x)
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| /third_party/flatbuffers/lua/flatbuffers/ |
| D | builder.lua | 237 local soffset = self:Offset()
238 if off <= soffset then
239 local off2 = soffset - off + 4
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 895 // These new instrinsics also keep the offset and soffset arguments separate as
901 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
916 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
931 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
947 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
962 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
984 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
995 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1018 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1029 llvm_i32_ty, // soffset(SGPR)
[all …]
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | r600_buffer_common.c | 492 unsigned soffset; in r600_buffer_do_flush_region() local
497 soffset = rtransfer->b.b.offset + box->x % R600_MAP_BUFFER_ALIGNMENT; in r600_buffer_do_flush_region()
499 u_box_1d(soffset, box->width, &dma_box); in r600_buffer_do_flush_region()
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| /third_party/flatbuffers/rust/flatbuffers/src/ |
| D | verifier.rs | 80 soffset: SOffsetT,
313 soffset: offset, in deref_soffset()
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_assembler.cpp | 242 uint32_t soffset = ctx.chip_class >= GFX10 in emit_instruction() local
256 soffset = op_off1.physReg(); in emit_instruction()
266 soffset = op_off2.physReg(); in emit_instruction()
270 encoding |= soffset << 25; in emit_instruction()
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| D | aco_instruction_selection.cpp | 3649 Temp soffset = Temp(0, s1); member
4038 Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand::c32(0); in mubuf_load_callback() local
4040 if (info.soffset.id()) { in mubuf_load_callback()
4041 if (soffset.isTemp()) in mubuf_load_callback()
4042 vaddr = bld.copy(bld.def(v1), soffset); in mubuf_load_callback()
4043 soffset = Operand(info.soffset); in mubuf_load_callback()
4070 mubuf->operands[2] = soffset; in mubuf_load_callback()
4557 emit_single_mubuf_store(isel_context* ctx, Temp descriptor, Temp voffset, Temp soffset, Temp vdata, in emit_single_mubuf_store() argument
4570 Operand soffset_op = soffset.id() ? Operand(soffset) : Operand::zero(); in emit_single_mubuf_store()
4581 store_vmem_mubuf(isel_context* ctx, Temp src, Temp descriptor, Temp voffset, Temp soffset, in store_vmem_mubuf() argument
[all …]
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| /third_party/alsa-lib/src/ucm/ |
| D | main.c | 992 unsigned long soffset, in find0() argument
1000 str = *((char **)(ptr + soffset)); in find0()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_nir_to_llvm.c | 2737 LLVMValueRef value, soffset; in ac_gs_copy_shader_emit() local
2742 soffset = LLVMConstInt(ctx->ac.i32, offset * ctx->shader->info.gs.vertices_out * 16 * 4, in ac_gs_copy_shader_emit()
2748 soffset, 0, ctx->ac.f32, ac_glc | ac_slc, true, false); in ac_gs_copy_shader_emit()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.0.0.rst | 758 - aco: use soffset for MUBUF instructions on SI/CI
|