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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepMapAsm2Intrin.td14 def: Pat<(int_hexagon_S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
15 (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
16 def: Pat<(int_hexagon_S2_vsatwh DoubleRegs:$src1),
17 (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>;
18 def: Pat<(int_hexagon_M2_mpysu_up IntRegs:$src1, IntRegs:$src2),
19 (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
20 def: Pat<(int_hexagon_M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
21 (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
22 def: Pat<(int_hexagon_M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
23 (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
[all …]
DHexagonMapAsm2IntrinV65.gen.td9 …at<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), (A6_vcmpbeq_notany DoubleRe…
10 …ef: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat …
11 …at<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat …
12 …ef: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat …
13 …at<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat …
14 …Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsa…
15 …int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsa…
16 def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX]>;
17 def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX…
18 def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, Use…
[all …]
DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
13 (MI HvxVR:$src1, IntRegs:$src2)>;
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
[all …]
DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
22 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
25 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
28 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
29 (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
DHexagonIntrinsics.td127 def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred_timm:$src2),
128 (C2_tfrpr (C2_cmpgti I32:$src1, (SDEC1 s32_0ImmPred:$src2)))>;
130 def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32_0ImmPred_timm:$src2),
131 (C2_tfrpr (C2_cmpgtui I32:$src1, (UDEC1 u32_0ImmPred:$src2)))>;
135 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
136 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
137 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
138 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
[all …]
/third_party/ffmpeg/tests/checkasm/
Dfixed_dsp.c35 src1[i] = sign_extend(rnd(), 24); \
40 static void check_vector_fmul(const int *src0, const int *src1) in check_vector_fmul() argument
45 declare_func(void, int *dst, const int *src0, const int *src1, int len); in check_vector_fmul()
47 call_ref(ref, src0, src1, BUF_SIZE); in check_vector_fmul()
48 call_new(new, src0, src1, BUF_SIZE); in check_vector_fmul()
51 bench_new(new, src0, src1, BUF_SIZE); in check_vector_fmul()
54 static void check_vector_fmul_add(const int *src0, const int *src1, const int *src2) in check_vector_fmul_add() argument
59 declare_func(void, int *dst, const int *src0, const int *src1, const int *src2, int len); in check_vector_fmul_add()
61 call_ref(ref, src0, src1, src2, BUF_SIZE); in check_vector_fmul_add()
62 call_new(new, src0, src1, src2, BUF_SIZE); in check_vector_fmul_add()
[all …]
Dfloat_dsp.c44 static void test_vector_fmul(const float *src0, const float *src1) in test_vector_fmul() argument
50 declare_func(void, float *dst, const float *src0, const float *src1, in test_vector_fmul()
53 call_ref(cdst, src0, src1, LEN); in test_vector_fmul()
54 call_new(odst, src0, src1, LEN); in test_vector_fmul()
56 double t = fabs(src0[i]) + fabs(src1[i]) + fabs(src0[i] * src1[i]) + 1.0; in test_vector_fmul()
64 bench_new(odst, src0, src1, LEN); in test_vector_fmul()
67 static void test_vector_dmul(const double *src0, const double *src1) in test_vector_dmul() argument
73 declare_func(void, double *dst, const double *src0, const double *src1, in test_vector_dmul()
76 call_ref(cdst, src0, src1, LEN); in test_vector_dmul()
77 call_new(odst, src0, src1, LEN); in test_vector_dmul()
[all …]
Dllviddsp.c50 uint8_t *src1 = av_mallocz_array(width, sizeof(uint8_t)); in check_add_bytes() local
53 init_buffer(src0, src1, uint8_t, width); in check_add_bytes()
61 call_new(dst1, src1, width); in check_add_bytes()
64 bench_new(dst1, src1, width); in check_add_bytes()
68 av_free(src1); in check_add_bytes()
78 uint8_t *src1 = av_mallocz_array(width, sizeof(uint8_t)); in check_add_median_pred() local
81 declare_func_emms(AV_CPU_FLAG_MMX, void, uint8_t *dst, const uint8_t *src1, in check_add_median_pred()
85 init_buffer(src0, src1, uint8_t, width); in check_add_median_pred()
96 call_new(dst1, src1, diff1, width, &A1, &B1); in check_add_median_pred()
99 bench_new(dst1, src1, diff1, width, &A1, &B1); in check_add_median_pred()
[all …]
/third_party/mindspore/mindspore/ccsrc/backend/kernel_compiler/cpu/nnacl/intrinsics/
Dms_simd_instructions.h56 #define MS_MLAQ_F32(src1, src2, src3) vmlaq_f32(src1, src2, src3) argument
63 #define MS_MULQ_F32(src1, src2) vmulq_f32(src1, src2) argument
64 #define MS_MULQ_EPI32(src1, src2) vmulq_s32(src1, src2) argument
66 #define MS_DIVQ_F32(src1, src2) vdivq_f32(src1, src2) argument
74 #define MS_DIVQ_F32(src1, src2) vmulq_f32(src1, vrecp(src2)) argument
76 #define MS_MULQ_N_F32(src1, src2) vmulq_n_f32(src1, src2) argument
77 #define MS_MULQ_N_EPI32(src1, src2) vmulq_n_s32(src1, src2) argument
78 #define MS_DIVQ_N_F32(src1, src2) vdivq_n_f32(src1, src2) argument
79 #define MS_SLLIQ_EPI32(src1, src2) vshlq_s32(src1, vmovq_n_s32(src2)) argument
82 #define MS_CMPGTQ_F32(src1, src2) vcgtq_f32(src1, src2) argument
[all …]
/third_party/mindspore/mindspore/ccsrc/backend/kernel_compiler/cpu/nnacl/fp32_grad/
Dactivation_grad.c24 int ReluGrad(const float *src0, const float *src1, size_t length, float *dst) { in ReluGrad() argument
29 float32x4_t src1_4 = vld1q_f32(src1 + i); in ReluGrad()
37 dst[i] = (src1[i] > 0.0f) ? src0[i] : 0.0f; in ReluGrad()
42 int Relu6Grad(const float *src0, const float *src1, size_t length, float *dst) { in Relu6Grad() argument
48 float32x4_t src1_4 = vld1q_f32(src1 + i); in Relu6Grad()
58 dst[i] = (src1[i] > 0.0f && src1[i] <= 6.0f) ? src0[i] : 0.0f; in Relu6Grad()
63 int LReluGrad(const float *src0, const float *src1, size_t length, float *dst, float alpha) { in LReluGrad() argument
65 dst[i] = src1[i] > 0.0f ? src0[i] : alpha * src0[i]; in LReluGrad()
70 int SigmoidGrad(const float *src0, const float *src1, size_t length, float *dst) { in SigmoidGrad() argument
72 dst[i] = src0[i] * (src1[i] * (1.0f - src1[i])); in SigmoidGrad()
[all …]
/third_party/mindspore/mindspore/ccsrc/backend/kernel_compiler/cpu/nnacl/fp16_grad/
Dactivation_grad.c28 int ReluFp16Grad(const float16_t *src0, const float16_t *src1, int length, float16_t *dst) { in ReluFp16Grad() argument
34 float16x8_t src1_v = vld1q_f16(src1 + i); in ReluFp16Grad()
41 dst[i] = (src1[i] > 0.0f) ? src0[i] : 0.0f; in ReluFp16Grad()
46 int Relu6Fp16Grad(const float16_t *src0, const float16_t *src1, int length, float16_t *dst) { in Relu6Fp16Grad() argument
52 float16x8_t src1_8 = vld1q_f16(src1 + i); in Relu6Fp16Grad()
62 dst[i] = (src1[i] > 0.0f && src1[i] <= 6.0f) ? src0[i] : 0.0f; in Relu6Fp16Grad()
67 int LReluFp16Grad(const float16_t *src0, const float16_t *src1, int length, float16_t *dst, float16… in LReluFp16Grad() argument
73 MS_FLOAT16X8 src1_8 = MS_LDQ_F16(src1 + i); in LReluFp16Grad()
78 dst[i] = src0[i] * (src1[i] * (1.0f - src1[i])); in LReluFp16Grad()
83 int SigmoidFp16Grad(const float16_t *src0, const float16_t *src1, int length, float16_t *dst) { in SigmoidFp16Grad() argument
[all …]
/third_party/mindspore/mindspore/ccsrc/backend/kernel_compiler/cpu/nnacl/intrinsics/sse/
DPostFuncBiasReluC4.c35 __m128 src1 = _mm_loadu_ps(src); in PostFuncBiasReluC4() local
40 src1 = _mm_add_ps(src1, bias1); in PostFuncBiasReluC4()
45 ActBlock4(&src1, &src2, &src3, &src4, relu_type == 1, relu_type == 3); in PostFuncBiasReluC4()
47 _mm_storeu_ps(dst_c4, src1); in PostFuncBiasReluC4()
57 __m128 src1 = _mm_loadu_ps(src); in PostFuncBiasReluC4() local
58 src1 = _mm_add_ps(src1, bias1); in PostFuncBiasReluC4()
60 ActBlock1(&src1, relu_type == 1, relu_type == 3); in PostFuncBiasReluC4()
62 _mm_storeu_ps(dst_c4, src1); in PostFuncBiasReluC4()
78 __m128 src1 = _mm_loadu_ps(src); in PostFuncBiasReluC4() local
80 src1 = _mm_add_ps(src1, bias1); in PostFuncBiasReluC4()
[all …]
DPostFuncBiasReluC8.c35 __m128 src1 = _mm_loadu_ps(src); in PostFuncBiasReluC8() local
43 src1 = _mm_add_ps(src1, bias1); in PostFuncBiasReluC8()
52 ActBlock8(&src1, &src2, &src3, &src4, &src5, &src6, &src7, &src8, relu_type); in PostFuncBiasReluC8()
54 _mm_storeu_ps(dst_c8, src1); in PostFuncBiasReluC8()
68 __m128 src1 = _mm_loadu_ps(src); in PostFuncBiasReluC8() local
70 src1 = _mm_add_ps(src1, bias1); in PostFuncBiasReluC8()
73 ActBlock2(&src1, &src2, relu_type == 1, relu_type == 3); in PostFuncBiasReluC8()
75 _mm_storeu_ps(dst_c8, src1); in PostFuncBiasReluC8()
91 __m128 src1 = _mm_loadu_ps(src); in PostFuncBiasReluC8() local
93 src1 = _mm_add_ps(src1, bias1); in PostFuncBiasReluC8()
[all …]
/third_party/ltp/tools/sparse/sparse-src/
Dsimplify.c352 kill_use(&insn->src1); in kill_insn()
498 replace_pseudo(insn, &insn->src1, src); in replace_with_unop()
546 pseudo_t old_a = in->src1; in replace_insn_pair()
548 pseudo_t old_1 = out->src1; in replace_insn_pair()
551 use_pseudo(in, a, &in->src1); in replace_insn_pair()
553 use_pseudo(out, in->target, &out->src1); in replace_insn_pair()
556 remove_usage(old_a, &in->src1); in replace_insn_pair()
558 remove_usage(old_1, &out->src1); in replace_insn_pair()
629 static pseudo_t eval_op(int op, unsigned size, pseudo_t src1, pseudo_t src2) in eval_op() argument
632 long long left = src1->value; in eval_op()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrXOP.td97 (ins VR128:$src1, VR128:$src2),
98 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
100 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
103 (ins VR128:$src1, i128mem:$src2),
104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
106 (vt128 (OpNode (vt128 VR128:$src1),
110 (ins i128mem:$src1, VR128:$src2),
111 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
113 (vt128 (OpNode (vt128 (load addr:$src1)),
119 (ins VR128:$src1, VR128:$src2),
[all …]
DX86InstrShiftRotate.td17 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
19 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
22 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16;
25 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32;
28 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
30 [(set GR64:$dst, (shl GR64:$src1, CL))]>;
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
[all …]
/third_party/flutter/skia/third_party/externals/sdl/src/audio/
DSDL_mixer.c148 Sint16 src1, src2; in SDL_MixAudioFormat() local
155 src1 = ((src[1]) << 8 | src[0]); in SDL_MixAudioFormat()
156 ADJUST_VOLUME(src1, volume); in SDL_MixAudioFormat()
159 dst_sample = src1 + src2; in SDL_MixAudioFormat()
179 Sint16 src1, src2; in SDL_MixAudioFormat()
186 src1 = ((src[0]) << 8 | src[1]); in SDL_MixAudioFormat()
187 ADJUST_VOLUME(src1, volume); in SDL_MixAudioFormat()
190 dst_sample = src1 + src2; in SDL_MixAudioFormat()
207 Uint16 src1, src2; in SDL_MixAudioFormat() local
213 src1 = ((src[1]) << 8 | src[0]); in SDL_MixAudioFormat()
[all …]
/third_party/pcre2/pcre2/src/sljit/
DsljitNativePPC_32.c45 sljit_s32 dst, sljit_s32 src1, sljit_s32 src2) in emit_single_op() argument
52 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
59 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
74 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
86 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
90 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
95 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
101 …return push_inst(compiler, ADD | OE(ALT_SET_FLAGS) | RC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2… in emit_single_op()
109 return push_inst(compiler, ADDIS | D(dst) | A(src1) | compiler->imm); in emit_single_op()
112 …FAIL_IF(push_inst(compiler, ADDIS | D(dst) | A(src1) | (((compiler->imm >> 16) & 0xffff) + ((compi… in emit_single_op()
[all …]
DsljitNativePPC_64.c130 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \
131 src1 = TMP_REG1; \
141 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \
142 src1 = TMP_REG1; \
146 sljit_s32 dst, sljit_s32 src1, sljit_s32 src2) in emit_single_op() argument
151 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
158 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
171 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
186 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
198 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
[all …]
/third_party/ffmpeg/libavcodec/mips/
Dsimple_idct_mmi.c62 #define IDCT_ROW_COND_DC(src1, src2) \ in ff_simple_idct_8_mmi() argument
63 "dmfc1 $11, "#src1" \n\t" \ in ff_simple_idct_8_mmi()
69 "punpcklhw $f30, "#src1", "#src2" \n\t" \ in ff_simple_idct_8_mmi()
70 "punpckhhw $f31, "#src1", "#src2" \n\t" \ in ff_simple_idct_8_mmi()
72 "punpcklhw "#src1", $f30, $f31 \n\t" \ in ff_simple_idct_8_mmi()
76 "pmaddhw $f30, "#src1", $f18 \n\t" \ in ff_simple_idct_8_mmi()
87 "pmaddhw $f30, "#src1", $f20 \n\t" \ in ff_simple_idct_8_mmi()
98 "pmaddhw $f30, "#src1", $f22 \n\t" \ in ff_simple_idct_8_mmi()
109 "pmaddhw $f30, "#src1", $f24 \n\t" \ in ff_simple_idct_8_mmi()
111 "paddw "#src1", $f30, $f31 \n\t" \ in ff_simple_idct_8_mmi()
[all …]
/third_party/skia/third_party/externals/swiftshader/src/Shader/
DShaderCore.hpp247 void add(Vector4f &dst, const Vector4f &src0, const Vector4f &src1);
248 void iadd(Vector4f &dst, const Vector4f &src0, const Vector4f &src1);
249 void sub(Vector4f &dst, const Vector4f &src0, const Vector4f &src1);
250 void isub(Vector4f &dst, const Vector4f &src0, const Vector4f &src1);
251 void mad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2);
252 void imad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2);
253 void mul(Vector4f &dst, const Vector4f &src0, const Vector4f &src1);
254 void imul(Vector4f &dst, const Vector4f &src0, const Vector4f &src1);
256 void div(Vector4f &dst, const Vector4f &src0, const Vector4f &src1);
257 void idiv(Vector4f &dst, const Vector4f &src0, const Vector4f &src1);
[all …]
DShaderCore.cpp766 void ShaderCore::add(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) in add() argument
768 dst.x = src0.x + src1.x; in add()
769 dst.y = src0.y + src1.y; in add()
770 dst.z = src0.z + src1.z; in add()
771 dst.w = src0.w + src1.w; in add()
774 void ShaderCore::iadd(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) in iadd() argument
776 dst.x = As<Float4>(As<Int4>(src0.x) + As<Int4>(src1.x)); in iadd()
777 dst.y = As<Float4>(As<Int4>(src0.y) + As<Int4>(src1.y)); in iadd()
778 dst.z = As<Float4>(As<Int4>(src0.z) + As<Int4>(src1.z)); in iadd()
779 dst.w = As<Float4>(As<Int4>(src0.w) + As<Int4>(src1.w)); in iadd()
[all …]
/third_party/ffmpeg/libavcodec/
Dlossless_videoencdsp.c28 static void diff_bytes_c(uint8_t *dst, const uint8_t *src1, const uint8_t *src2, intptr_t w) in diff_bytes_c() argument
33 if (((long)src1 | (long)src2) & (sizeof(long) - 1)) { in diff_bytes_c()
35 dst[i + 0] = src1[i + 0] - src2[i + 0]; in diff_bytes_c()
36 dst[i + 1] = src1[i + 1] - src2[i + 1]; in diff_bytes_c()
37 dst[i + 2] = src1[i + 2] - src2[i + 2]; in diff_bytes_c()
38 dst[i + 3] = src1[i + 3] - src2[i + 3]; in diff_bytes_c()
39 dst[i + 4] = src1[i + 4] - src2[i + 4]; in diff_bytes_c()
40 dst[i + 5] = src1[i + 5] - src2[i + 5]; in diff_bytes_c()
41 dst[i + 6] = src1[i + 6] - src2[i + 6]; in diff_bytes_c()
42 dst[i + 7] = src1[i + 7] - src2[i + 7]; in diff_bytes_c()
[all …]
/third_party/gstreamer/gstreamer/tests/check/gst/
Dgstvalue.c1086 GValue src1 = { 0 }; in GST_START_TEST() local
1091 g_value_init (&src1, G_TYPE_INT); in GST_START_TEST()
1092 g_value_set_int (&src1, 10); in GST_START_TEST()
1095 ret = gst_value_intersect (&dest, &src1, &src2); in GST_START_TEST()
1097 g_value_unset (&src1); in GST_START_TEST()
1100 g_value_init (&src1, G_TYPE_STRING); in GST_START_TEST()
1101 g_value_set_static_string (&src1, "YUY2"); in GST_START_TEST()
1111 fail_unless (gst_value_intersect (&dest, &src1, &src2)); in GST_START_TEST()
1115 g_value_unset (&src1); in GST_START_TEST()
1126 GValue src1 = { 0 }; in GST_START_TEST() local
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/third_party/mesa3d/src/compiler/nir/tests/
Dssa_def_bits_used_tests.cpp59 nir_ssa_def *src0, nir_ssa_def *src1) in build_alu_instr() argument
61 nir_ssa_def *def = nir_build_alu(&bld, op, src0, src1, NULL, NULL); in build_alu_instr()
84 nir_ssa_def *src1 = nir_imm_int(&bld, 0xffffffff); in TEST_F() local
86 nir_alu_instr *alu = build_alu_instr(nir_op_iand, src0, src1); in TEST_F()
95 ASSERT_TRUE(is_used_once(src1)); in TEST_F()
113 nir_ssa_def *src1 = nir_imm_int(&bld, 0xffffffff); in TEST_F() local
115 nir_alu_instr *alu = build_alu_instr(nir_op_ior, src0, src1); in TEST_F()
124 ASSERT_TRUE(is_used_once(src1)); in TEST_F()
141 nir_ssa_def *src1 = nir_imm_ivec4(&bld, in TEST_F() local
147 nir_alu_instr *alu = build_alu_instr(nir_op_extract_i16, src0, src1); in TEST_F()
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