| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | VOP2Instructions.td | 307 src0_sel:$src0_sel, src1_sel:$src1_sel);
346 …WA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
347 …A9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
360 …$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
361 …$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
376 src0_sel:$src0_sel, src1_sel:$src1_sel);
395 …A = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
396 …9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
412 src0_sel:$src0_sel, src1_sel:$src1_sel);
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| D | VOPCInstructions.td | 70 src0_sel:$src0_sel, src1_sel:$src1_sel);
73 let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
629 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
631 let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel";
643 src0_sel:$src0_sel, src1_sel:$src1_sel);
645 let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
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| D | R600InstrFormats.td | 89 bits<9> src1_sel = src1{8-0};
95 let Word0{21-13} = src1_sel;
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| D | VOPInstructions.td | 401 bits<3> src1_sel;
414 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
437 bits<3> src1_sel;
446 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
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| D | SIInstrInfo.td | 1090 def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>;
1843 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1851 src0_sel:$src0_sel, src1_sel:$src1_sel),
1857 src0_sel:$src0_sel, src1_sel:$src1_sel))),
2013 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
2014 " $dst_sel $dst_unused $src0_sel $src1_sel"
2041 … " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
2042 out_mods#" $dst_sel $dst_unused $src0_sel $src1_sel"
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| D | R600InstrInfo.cpp | 257 {R600::OpName::src1, R600::OpName::src1_sel}, in getSelIdx()
310 {R600::OpName::src1, R600::OpName::src1_sel}, in getSrcs()
1307 OPERAND_CASE(R600::OpName::src1_sel) in getSlotedOps()
1346 R600::OpName::src1_sel, in buildSlotOfVectorInstruction()
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| D | SIPeepholeSDWA.cpp | 377 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
1115 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1_sel) != -1); in convertToSDWA()
1116 MachineOperand *Src1Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
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| D | EvergreenInstructions.td | 554 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
586 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
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| D | R600Instructions.td | 150 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
190 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
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| /third_party/mesa3d/src/freedreno/ir2/ |
| D | instr-a2xx.h | 173 uint8_t src1_sel : 1; member
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| D | disasm-a2xx.c | 261 print_srcreg(alu->src1_reg, alu->src1_sel, alu->src1_swiz, in disasm_alu()
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| D | ir2_assemble.c | 282 bc->alu.src1_sel = src1.type != IR2_SRC_CONST; in fill_instr()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 814 int src1_sel, unsigned src1_chan_val) in single_alu_op2() argument
828 alu.src[1].sel = src1_sel; in single_alu_op2()
829 if (src1_sel == V_SQ_ALU_SRC_LITERAL) in single_alu_op2()
851 alu.src[1].sel = src1_sel; in single_alu_op2()
852 if (src1_sel == V_SQ_ALU_SRC_LITERAL) in single_alu_op2()
870 int src1_sel, unsigned src1_chan_val, in single_alu_op3() argument
885 alu.src[1].sel = src1_sel; in single_alu_op3()
886 if (src1_sel == V_SQ_ALU_SRC_LITERAL) in single_alu_op3()
11009 int src1_sel, int src1_chan) in emit_u64add() argument
11027 alu.src[1].sel = src1_sel; in emit_u64add()
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