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Searched refs:subreg (Results 1 – 25 of 26) sorted by relevance

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/third_party/mesa3d/src/intel/compiler/
Dbrw_eu_validate.c861 unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); in general_restrictions_based_on_operand_types() local
862 ERROR_IF(subreg % 4 != 0, in general_restrictions_based_on_operand_types()
867 unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); in general_restrictions_based_on_operand_types() local
870 dst_stride == 1 && subreg % 16 == 0), in general_restrictions_based_on_operand_types()
894 unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); in general_restrictions_based_on_operand_types() local
904 ERROR_IF(subreg % exec_type_size != 0 && in general_restrictions_based_on_operand_types()
905 subreg % exec_type_size != 1, in general_restrictions_based_on_operand_types()
910 ERROR_IF(subreg % exec_type_size != 0, in general_restrictions_based_on_operand_types()
982 unsigned vstride, width, hstride, element_size, subreg; in general_restrictions_on_region_parameters() local
995 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst) in general_restrictions_on_region_parameters()
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Dbrw_reg.h898 brw_flag_reg(int reg, int subreg) in brw_flag_reg() argument
901 BRW_ARF_FLAG + reg, subreg); in brw_flag_reg()
905 brw_flag_subreg(unsigned subreg) in brw_flag_subreg() argument
908 BRW_ARF_FLAG + subreg / 2, subreg % 2); in brw_flag_subreg()
Dbrw_eu.cpp172 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg) in brw_set_default_flag_reg() argument
174 assert(subreg < 2); in brw_set_default_flag_reg()
175 p->current->flag_subreg = reg * 2 + subreg; in brw_set_default_flag_reg()
Dbrw_eu.h170 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
Dbrw_fs.cpp5614 const unsigned subreg = sample_mask_flag_subreg(v); in emit_predicate_on_sample_mask() local
5618 sample_mask.nr == brw_flag_subreg(subreg).nr && in emit_predicate_on_sample_mask()
5620 subreg + inst->group / 16).subnr); in emit_predicate_on_sample_mask()
5623 .MOV(brw_flag_subreg(subreg + inst->group / 16), sample_mask); in emit_predicate_on_sample_mask()
5635 inst->flag_subreg = subreg; in emit_predicate_on_sample_mask()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td28 class RISCVReg64<RISCVReg32 subreg> : Register<""> {
29 let HWEncoding{4-0} = subreg.HWEncoding{4-0};
30 let SubRegs = [subreg];
32 let AsmName = subreg.AsmName;
33 let AltNames = subreg.AltNames;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td44 // subreg of the result.
1567 // vector register. Scalar to vector conversion is just a subreg and
1570 SubRegIndex subreg> {
1572 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>;
1575 subreg), 0)>;
1593 // than 0) and then taking a high subreg. The AddedComplexity counters the
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/
DCREDITS.TXT243 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DREADME.txt623 - Each CR subreg is saved individually, rather than doing one save as a unit.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DTargetOpcodes.def88 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DREADME.txt28 But that requires good 8-bit subreg support.
31 shorter, and doesn't stress 8-bit subreg support.
DX86RegisterInfo.td440 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
DX86InstrAVX512.td4060 SubRegIndex subreg> {
4067 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
4079 SubRegIndex subreg> {
4087 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
4093 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
4123 SubRegIndex subreg> {
4130 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
4140 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
4152 SubRegIndex subreg> {
4159 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARM.td245 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
DARMInstrNEON.td2467 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2472 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2477 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2482 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2489 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2496 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTarget.td543 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
546 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips64InstrInfo.td814 // lower subreg would not be replicated into the upper half.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td2092 //:FIXME: i think it's better to emit an extract subreg node in the DAG than
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2819 // Match stores from lane 0 to the appropriate subreg's store.
2947 // Match stores from lane 0 to the appropriate subreg's store.
3084 // Match stores from lane 0 to the appropriate subreg's store.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenRegisterInfo.inc5500 assert(Idx < 6 && "Bad subreg");
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenRegisterInfo.inc7140 assert(Idx < 11 && "Bad subreg");
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc9598 assert(Idx < 10 && "Bad subreg");
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc15647 assert(Idx < 56 && "Bad subreg");
DARMGenDAGISel.inc65522 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
65536 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
65593 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
65607 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
65615 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
65623 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc20059 assert(Idx < 99 && "Bad subreg");

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