| /third_party/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_wm_surface_state.c | 141 uint32_t *surf_offset, int surf_index, in brw_emit_surface_state() argument
175 surf_offset); in brw_emit_surface_state()
179 *surf_offset + brw->isl_dev.ss.addr_offset, in brw_emit_surface_state()
202 *surf_offset + in brw_emit_surface_state()
209 *surf_offset + in brw_emit_surface_state()
223 *surf_offset + in brw_emit_surface_state()
466 uint32_t *surf_offset, in brw_update_texture_surface() argument
476 brw_update_buffer_texture_surface(ctx, unit, surf_offset); in brw_update_texture_surface()
586 const int surf_index = surf_offset - &brw->wm.base.surf_offset[0]; in brw_update_texture_surface()
618 surf_offset, surf_index, in brw_update_texture_surface()
[all …]
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| D | gfx6_sol.c | 62 &brw->gs.base.surf_offset[surf_index], in gfx6_update_sol_surfaces()
68 &brw->ff_gs.surf_offset[surf_index], in gfx6_update_sol_surfaces()
74 brw->ff_gs.surf_offset[surf_index] = 0; in gfx6_update_sol_surfaces()
76 brw->gs.base.surf_offset[surf_index] = 0; in gfx6_update_sol_surfaces()
140 memcpy(bind, brw->ff_gs.surf_offset, in brw_gs_upload_binding_table()
168 memcpy(bind, brw->gs.base.surf_offset, in brw_gs_upload_binding_table()
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| D | gfx6_constant_state.c | 242 if (stage_state->surf_offset[surf_index]) { in brw_upload_pull_constants()
243 stage_state->surf_offset[surf_index] = 0; in brw_upload_pull_constants()
275 brw_emit_buffer_surface_state(brw, &stage_state->surf_offset[surf_index], in brw_upload_pull_constants()
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| D | brw_binding_tables.c | 71 brw, &stage_state->surf_offset[ in brw_upload_binding_table()
81 memcpy(bind, stage_state->surf_offset, in brw_upload_binding_table()
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| D | brw_context.h | 644 uint32_t surf_offset[BRW_MAX_SURFACES]; member
1116 uint32_t surf_offset[BRW_MAX_SOL_BINDINGS]; member
1406 uint32_t *surf_offset);
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| D | genX_state_upload.c | 4278 brw, &stage_state->surf_offset[
4374 memcpy(bind, stage_state->surf_offset,
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| /third_party/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_vcn_dec_jpeg.c | 47 dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset; in radeon_jpeg_get_decode_param()
49 dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset; in radeon_jpeg_get_decode_param()
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| D | radeon_vcn_enc_1_2.c | 1170 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_enc_encode_params()
1171 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_enc_encode_params()
1220 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_enc_encode_params_hevc()
1221 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_enc_encode_params_hevc()
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| D | radeon_vce_52.c | 274 enc->luma->u.gfx9.surf_offset); // inputPictureLumaAddressHi/Lo in encode()
276 enc->chroma->u.gfx9.surf_offset); // inputPictureChromaAddressHi/Lo in encode()
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| D | radeon_uvd_enc_1_1.c | 904 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_uvd_enc_encode_params_hevc()
905 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_uvd_enc_encode_params_hevc()
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| D | radeon_vcn_dec.c | 1679 decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset; in rvcn_dec_message_decode()
1680 decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset; in rvcn_dec_message_decode()
1683 luma->surface.u.gfx9.surf_offset + luma->surface.u.gfx9.surf_slice_size; in rvcn_dec_message_decode()
1685 chroma->surface.u.gfx9.surf_offset + chroma->surface.u.gfx9.surf_slice_size; in rvcn_dec_message_decode()
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| D | radeon_uvd.c | 1386 return surface->u.gfx9.surf_offset + layer * surface->u.gfx9.surf_slice_size; in texture_offset()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_sdma_copy_image.c | 116 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset; in si_sdma_v4_v5_copy_texture()
117 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.gfx9.surf_offset; in si_sdma_v4_v5_copy_texture()
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| D | si_state.c | 2562 assert(tex->surface.u.gfx9.surf_offset == 0); in si_init_depth_surface()
3125 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8; in si_emit_framebuffer_state()
3172 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8; in si_emit_framebuffer_state()
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| D | si_texture.c | 134 return tex->surface.u.gfx9.surf_offset + box->z * tex->surface.u.gfx9.surf_slice_size + in si_texture_get_offset()
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| D | si_descriptors.c | 307 va += tex->surface.u.gfx9.surf_offset; in si_set_mutable_tex_desc_fields()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface.h | 238 uint64_t surf_offset; /* 0 unless imported with an offset */ member
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| D | ac_surface.c | 2230 surf->u.gfx9.surf_offset = 0; in gfx9_compute_surface()
2616 offset = surf->u.gfx9.surf_offset; in ac_surface_set_umd_metadata()
2809 surf->u.gfx9.surf_offset = offset; in ac_surface_override_offset_stride()
2862 return surf->u.gfx9.surf_offset + in ac_surface_get_plane_offset()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.0.7.rst | 71 - i965: Fix out-of-bounds access to brw_stage_state::surf_offset
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| D | 20.0.0.rst | 2693 - radeonsi: use gfx9.surf_offset to compute texture offset
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| D | 19.3.0.rst | 2738 - radeonsi: use gfx9.surf_offset to compute texture offset
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| /third_party/mesa3d/src/gallium/drivers/crocus/ |
| D | crocus_context.h | 396 uint32_t surf_offset[128];//TODO member
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| D | crocus_state.c | 5384 uint32_t *surf_offsets = shader->surf_offset; in crocus_populate_binding_table()
6306 ice->shaders.prog[stage]->surf_offset,
6321 ice->shaders.ff_gs_prog->surf_offset,
8062 ice->shaders.prog[MESA_SHADER_COMPUTE]->surf_offset,
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 735 va += plane->surface.u.gfx9.surf_offset; in si_set_mutable_tex_desc_fields()
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| D | radv_device.c | 6631 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8; in radv_initialise_color_surface()
6926 assert(surf->u.gfx9.surf_offset == 0); in radv_initialise_ds_surface()
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