| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_state_binning.c | 343 const unsigned fragmentsLog2 = util_logbase2(num_fragments); in gfx10_get_bin_sizes()
344 const unsigned samplesLog2 = util_logbase2(num_samples); in gfx10_get_bin_sizes()
358 const unsigned colorLog2Pixels = util_logbase2(colorBinSizeTagPart / cColor); in gfx10_get_bin_sizes()
368 const unsigned fmaskLog2Pixels = util_logbase2(fmaskBinSizeTagPart / cFmask); in gfx10_get_bin_sizes()
396 const unsigned depthLog2Pixels = util_logbase2(depthBinSizeTagPart / MAX2(cDepth, 1u)); in gfx10_get_bin_sizes()
417 bin_size_extend.x = util_logbase2(bin_size.x) - 5; in si_emit_dpbb_disable()
419 bin_size_extend.y = util_logbase2(bin_size.y) - 5; in si_emit_dpbb_disable()
501 bin_size_extend.x = util_logbase2(bin_size.x) - 5; in si_emit_dpbb_state()
503 bin_size_extend.y = util_logbase2(bin_size.y) - 5; in si_emit_dpbb_state()
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| D | si_test_dma_perf.c | 259 struct si_result *r = &results[util_logbase2(size)][placement][method]; in si_test_dma_perf()
326 struct si_result *r = &results[util_logbase2(size)][placement][i]; in si_test_dma_perf()
386 &results[util_logbase2(size)][placement][prev->index]; in si_test_dma_perf()
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| D | si_sdma_copy_image.c | 61 return util_logbase2(tex->surface.bpe) | in encode_legacy_tile_info()
65 ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) | in encode_legacy_tile_info()
188 radeon_emit(util_logbase2(bpp) | in si_sdma_v4_v5_copy_texture()
270 (util_logbase2(bpp) << 29)); in cik_sdma_copy_texture()
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| D | si_compute_blit.c | 668 unsigned bpe_log2 = util_logbase2(tex->surface.bpe); in gfx9_clear_dcc_msaa()
669 unsigned log2_samples = util_logbase2(tex->buffer.b.b.nr_samples); in gfx9_clear_dcc_msaa()
700 unsigned log_fragments = util_logbase2(tex->nr_storage_samples); in si_compute_expand_fmask()
701 unsigned log_samples = util_logbase2(tex->nr_samples); in si_compute_expand_fmask()
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| /third_party/mesa3d/src/panfrost/lib/ |
| D | pan_tiler.c | 211 #define MIN_TILE_SHIFT util_logbase2(MIN_TILE_SIZE)
212 #define MAX_TILE_SHIFT util_logbase2(MAX_TILE_SIZE)
347 unsigned exp_w = util_logbase2(best_w / 16); in panfrost_choose_tile_size()
348 unsigned exp_h = util_logbase2(best_h / 16); in panfrost_choose_tile_size()
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| D | pan_attributes.c | 100 unsigned shift = util_logbase2(hw_divisor); in panfrost_compute_magic_divisor()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface_meta_address_test.c | 72 unsigned meta_block_width_log2 = util_logbase2(meta_block_width); in gfx9_meta_addr_from_coord()
73 unsigned meta_block_height_log2 = util_logbase2(meta_block_height); in gfx9_meta_addr_from_coord()
74 unsigned meta_block_depth_log2 = util_logbase2(meta_block_depth); in gfx9_meta_addr_from_coord()
133 unsigned meta_block_width_log2 = util_logbase2(meta_block_width); in gfx10_meta_addr_from_coord()
134 unsigned meta_block_height_log2 = util_logbase2(meta_block_height); in gfx10_meta_addr_from_coord()
183 unsigned bpp_log2 = util_logbase2(bpp >> 3); in gfx10_dcc_addr_from_coord()
184 unsigned meta_block_width_log2 = util_logbase2(meta_block_width); in gfx10_dcc_addr_from_coord()
185 unsigned meta_block_height_log2 = util_logbase2(meta_block_height); in gfx10_dcc_addr_from_coord()
242 xin.format = format[util_logbase2(bpp / 8)]; in one_dcc_address_test()
391 unsigned meta_block_width_log2 = util_logbase2(meta_block_width); in gfx10_htile_addr_from_coord()
[all …]
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| D | ac_surface.c | 695 …surf->meta_alignment_log2 = MAX2(surf->meta_alignment_log2, util_logbase2(AddrDccOut->dccRamBaseAl… in gfx6_compute_level()
773 surf->meta_alignment_log2 = util_logbase2(AddrHtileOut->baseAlign); in gfx6_compute_level()
846 surf->surf_alignment_log2 = util_logbase2(csio->baseAlign); in gfx6_surface_settings()
947 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in ac_compute_cmask()
1265 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign); in gfx6_compute_surface()
1666 surf->surf_alignment_log2 = MAX2(surf->surf_alignment_log2, util_logbase2(out.baseAlign)); in gfx9_compute_miptree()
1687 surf->surf_alignment_log2 = util_logbase2(out.baseAlign); in gfx9_compute_miptree()
1750 surf->meta_alignment_log2 = util_logbase2(hout.baseAlign); in gfx9_compute_miptree()
1845 surf->meta_alignment_log2 = util_logbase2(dout.dccRamBaseAlign); in gfx9_compute_miptree()
1918 surf->u.gfx9.color.display_dcc_alignment_log2 = util_logbase2(dout.dccRamBaseAlign); in gfx9_compute_miptree()
[all …]
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| /third_party/mesa3d/src/gallium/drivers/nouveau/nv30/ |
| D | nv30_clear.c | 123 rt_format |= util_logbase2(sf->width) << 16; in nv30_clear_render_target()
124 rt_format |= util_logbase2(sf->height) << 24; in nv30_clear_render_target()
183 rt_format |= util_logbase2(sf->width) << 16; in nv30_clear_depth_stencil()
184 rt_format |= util_logbase2(sf->height) << 24; in nv30_clear_depth_stencil()
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| D | nv30_texture.c | 299 so->fmt |= util_logbase2(pt->width0) << 20; in nv30_sampler_view_create()
300 so->fmt |= util_logbase2(pt->height0) << 24; in nv30_sampler_view_create()
301 so->fmt |= util_logbase2(pt->depth0) << 28; in nv30_sampler_view_create()
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| D | nv30_transfer.c | 190 format |= util_logbase2(dst->w) << 16; in nv30_transfer_rect_blit()
191 format |= util_logbase2(dst->h) << 24; in nv30_transfer_rect_blit()
453 PUSH_DATA (push, ss_fmt | (util_logbase2(dst->w) << 16) | in nv30_transfer_rect_sifm()
454 (util_logbase2(dst->h) << 24)); in nv30_transfer_rect_sifm()
571 unsigned k = util_logbase2(MIN2(rect->w, rect->h)); in swizzle2d_ptr()
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| D | nv30_state_validate.c | 96 rt_format |= util_logbase2(w) << 16; in nv30_validate_fb()
97 rt_format |= util_logbase2(h) << 24; in nv30_validate_fb()
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| /third_party/mesa3d/src/freedreno/vulkan/ |
| D | tu_nir_lower_multiview.c | 31 *mask = BIT(util_logbase2(old_mask) + 1) - 1; in lower_multiview_mask()
84 unsigned num_views = util_logbase2(mask) + 1; in tu_nir_lower_multiview()
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| D | tu_util.h | 39 return util_logbase2(samples); in tu_msaa_samples()
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| /third_party/mesa3d/src/gallium/frontends/lavapipe/ |
| D | lvp_formats.c | 209 maxMipLevels = util_logbase2(max_2d_ext) + 1; in lvp_get_image_format_properties()
216 maxMipLevels = util_logbase2(max_2d_ext) + 1; in lvp_get_image_format_properties()
228 maxMipLevels = util_logbase2(max_2d_ext) + 1; in lvp_get_image_format_properties()
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| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 191 surf_ws->surf_alignment_log2 = util_logbase2(surf_drm->bo_alignment); in surf_drm_to_winsys()
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
407 surf_ws->fmask_alignment_log2 = util_logbase2(MAX2(256, 1 << fmask.surf_alignment_log2)); in radeon_winsys_surface_init()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | cayman_msaa.c | 235 unsigned log_samples = util_logbase2(setup_samples); in cayman_emit_msaa_state()
237 util_logbase2(util_next_power_of_two(ps_iter_samples)); in cayman_emit_msaa_state()
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| /third_party/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_emit_gv100.cpp | 222 emitField(84, 2, util_logbase2(typeSizeof(insn->sType))); in emitF2F()
225 emitField(75, 2, util_logbase2(typeSizeof(insn->dType))); in emitF2F()
236 emitField(84, 2, util_logbase2(typeSizeof(insn->sType))); in emitF2I()
240 emitField(75, 2, util_logbase2(typeSizeof(insn->dType))); in emitF2I()
273 emitField(84, 2, util_logbase2(typeSizeof(insn->sType))); in emitFRND()
276 emitField(75, 2, util_logbase2(typeSizeof(insn->dType))); in emitFRND()
286 emitField(84, 2, util_logbase2(typeSizeof(insn->sType))); in emitI2F()
288 emitField(75, 2, util_logbase2(typeSizeof(insn->dType))); in emitI2F()
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| /third_party/mesa3d/src/util/ |
| D | u_math.h | 392 util_logbase2(unsigned n) in util_logbase2() function
434 return 1 + util_logbase2(n - 1); in util_logbase2_ceil()
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| /third_party/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_clip.c | 115 key.nr_userclip = util_logbase2(ctx->Transform.ClipPlanesEnabled) + 1; in brw_upload_clip_prog()
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| /third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_bo.c | 934 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw)); in radv_amdgpu_winsys_bo_set_metadata()
935 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->u.legacy.bankh)); in radv_amdgpu_winsys_bo_set_metadata()
939 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea)); in radv_amdgpu_winsys_bo_set_metadata()
940 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks) - 1); in radv_amdgpu_winsys_bo_set_metadata()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_ir_fs.h | 300 const int delta = util_logbase2(type_sz(reg.type)) - in subscript()
301 util_logbase2(type_sz(type)); in subscript()
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| /third_party/mesa3d/src/panfrost/midgard/ |
| D | midgard_ra.c | 491 int comps1 = util_logbase2(ins->mask); in allocate_registers()
693 util_logbase2(nir_alu_type_get_type_size(ins->src_types[i]) / 8); in install_registers_instr()
697 util_logbase2(nir_alu_type_get_type_size(ins->dest_type) / 8); in install_registers_instr()
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| /third_party/mesa3d/src/gallium/drivers/r300/ |
| D | r300_texture_desc.c | 68 tile = table[macrotile][util_logbase2(pixsize)][microtile][dim]; in r300_get_pixel_alignment()
72 h_tile = table[macrotile][util_logbase2(pixsize)][microtile][DIM_HEIGHT]; in r300_get_pixel_alignment()
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| /third_party/mesa3d/src/gallium/auxiliary/pipebuffer/ |
| D | pb_bufmgr_mm.c | 196 mm_buf->base.alignment_log2 = util_logbase2(desc->alignment); in mm_bufmgr_create_buffer()
|