v1b (reference) in projects: third_party

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Searched refs:v1b (Results 1 – 9 of 9) sorted by relevance

/third_party/mesa3d/src/amd/compiler/tests/
D	test_to_hw_instr.cpp	`150 Definition(v0_lo, v1b), Definition(v1_lo, v1b), 151 Operand(v1_lo, v1b), Operand(v0_lo, v1b)); 160 Operand(v1_lo, v1b), Operand(v0_lo, v1b)); 170 Definition(v0_lo, v3b), Operand(v1_lo, v1b), 171 Operand(v0_lo, v1b), Operand(v2_lo, v1b)); 184 Operand(v1_lo, v1b), Operand(v0_lo, v1b), 185 Operand(v2_lo, v1b), Operand(v3_lo, v1b)); 198 Operand(v0_lo, v1b), Operand(v0_lo, v1b), 199 Operand(v0_lo, v1b), Operand(v0_lo, v1b)); 207 Definition(v1_lo, v1b), Definition(v0_lo, v1b), [all …]`
D	test_regalloc.cpp	`155 Temp tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), inputs[0], Operand::zero()); 173 Temp tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), inputs[0], Operand::c32(4u));`
D	test_sdwa.cpp	`40 … sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1b), inputs[0], inputs[1]).instr->sdwa();`
/third_party/mesa3d/docs/relnotes/
D	21.1.3.rst	`123 - aco: use v1b/v2b for ds_read_u8/ds_read_u16`
D	21.3.0.rst	`3582 - aco/ra: allow v1b operands with 16-bit instructions`
D	21.2.0.rst	`4451 - aco: use v1b/v2b for ds_read_u8/ds_read_u16`
/third_party/mesa3d/src/amd/compiler/
D	aco_lower_to_hw_instr.cpp	`513 if (src.regClass() == v1b) { in emit_reduction() 1067 assert(dst.regClass() == v1b \|\| dst.regClass() == v2b); in copy_constant() 1069 if (dst.regClass() == v1b && ctx->program->chip_class >= GFX9) { in copy_constant() 1267 tmp.op = Operand(op, v1b); in do_swap() 1268 tmp.def = Definition(def, v1b); in do_swap() 2143 assert(dst.regClass() == v2b \|\| dst.regClass() == v1b \|\| op.regClass() == v2b \|\| in lower_to_hw_instr() 2144 op.regClass() == v1b); in lower_to_hw_instr()`
D	aco_ir.h	`326 v1b = v1 \| (1 << 7), enumerator 393 static constexpr RegClass v1b{RegClass::v1b};`
D	aco_instruction_selection.cpp	1428 if (dst.regClass() == v1 \|\| dst.regClass() == v2b \|\| dst.regClass() == v1b) { in visit_alu_instr() 1557 } else if (dst.regClass() == v1 \|\| dst.regClass() == v2b \|\| dst.regClass() == v1b) { in visit_alu_instr() 1573 } else if (dst.regClass() == v1 \|\| dst.regClass() == v2b \|\| dst.regClass() == v1b) { in visit_alu_instr() 1589 } else if (dst.regClass() == v1 \|\| dst.regClass() == v2b \|\| dst.regClass() == v1b) { in visit_alu_instr() 2494 tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), tmp, Operand::zero()); in visit_alu_instr() 8295 if (src.regClass() == v1b \|\| src.regClass() == v2b) { in visit_intrinsic() 8300 bld.def(src.regClass() == v1b ? v3b : v2b), tmp); in visit_intrinsic() 8347 if (src.regClass() == v1b \|\| src.regClass() == v2b \|\| src.regClass() == v1) { in visit_intrinsic() 8583 } else if (dst.regClass() == v1b) { in visit_intrinsic()