| /third_party/ffmpeg/libavcodec/arm/ |
| D | mdct_vfp.S | 47 vldr d8, [TCOS, #trig_lo*4] @ s16,s17 define
48 vldr d9, [TCOS, #trig_hi*4] @ s18,s19 define
49 vldr s0, [IN, #in_hi*4 + 12]
50 vldr s1, [IN, #in_hi*4 + 4]
51 vldr s2, [IN, #in_lo*4 + 12]
52 vldr s3, [IN, #in_lo*4 + 4]
54 vldr d10, [TSIN, #trig_lo*4] @ s20,s21
55 vldr d11, [TSIN, #trig_hi*4] @ s22,s23
56 vldr s4, [IN, #in_lo*4]
57 vldr s5, [IN, #in_lo*4 + 8]
[all …]
|
| D | fft_vfp.S | 55 vldr d0, [a1, #0*2*4] @ s0,s1 = z[0] define
56 vldr d4, [a1, #1*2*4] @ s8,s9 = z[1] define
57 vldr d1, [a1, #2*2*4] @ s2,s3 = z[2] define
58 vldr d5, [a1, #3*2*4] @ s10,s11 = z[3] define
92 vldr d4, [a1, #0 * 2*4] define
93 vldr d6, [a1, #1 * 2*4] define
94 vldr d5, [a1, #2 * 2*4] define
95 vldr d7, [a1, #3 * 2*4] define
97 vldr d12, [a1, #4 * 2*4]
99 vldr d14, [a1, #5 * 2*4]
[all …]
|
| D | synth_filter_vfp.S | 70 vldr d8, [P_SB, #OFFSET] @ d8 = SBUF_DAT define
71 vldr d9, [P_SB, #OFFSET+8] define
79 vldr d10, [P_SB, #OFFSET] @ d10 = SBUF_DAT_ALT
80 vldr d11, [P_SB, #OFFSET+8]
91 vldr d14, [P_WIN_UP, #OFFSET] @ d14 = WIN_UP_DAT
92 vldr d15, [P_WIN_UP, #OFFSET+8]
93 vldr d12, [P_WIN_DN, #OFFSET] @ d12 = WIN_DN_DAT
94 vldr d13, [P_WIN_DN, #OFFSET+8]
144 NOVFP vldr SCALE, [sp, #(16+6+3)*4]
180 vldr.d d4, zero @ d4 = VC0
[all …]
|
| D | synth_filter_neon.S | 43 NOVFP vldr s0, [sp, #12*4] @ scale
|
| /third_party/optimized-routines/string/arm/ |
| D | memcpy.S | 87 vldr \vreg, [src, #\base]
89 vldr d0, [src, #\base + 8] define
91 vldr d1, [src, #\base + 16] define
93 vldr d2, [src, #\base + 24] define
95 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
97 vldr d0, [src, #\base + 40] define
99 vldr d1, [src, #\base + 48] define
101 vldr d2, [src, #\base + 56] define
106 vldr \vreg, [src, #\base]
108 vldr d0, [src, #\base + 8] define
[all …]
|
| /third_party/mindspore/mindspore/ccsrc/backend/kernel_compiler/cpu/nnacl/assembly/arm82_aarch32_fp16/ |
| D | Float32ToFloat16.S | 61 vldr s0, [r0]
|
| D | Float16Tofloat32.S | 61 vldr.16 s0, [r0]
|
| /third_party/openh264/codec/encoder/core/arm/ |
| D | intra_pred_neon.S | 99 vldr d0, [r3] define
435 vldr d0, [r3] define
484 vldr d1, [r3] define
|
| /third_party/openh264/codec/decoder/core/arm/ |
| D | intra_pred_neon.S | 142 vldr d0, [r2] define
481 vldr d0, [r2] define
530 vldr d1, [r2] define
|
| /third_party/ffmpeg/libavresample/arm/ |
| D | resample_neon.S | 341 vldr s0, [sp, #12] /* frac */
|
| /third_party/openssl/crypto/chacha/asm/arm32/ |
| D | chacha-armv4.S | 1098 vldr d24,[sp,#4*(16+0)] @ one
1103 vldr d26,[sp,#4*(16+2)] @ two
1140 vldr d24,[sp,#4*(16+4)] @ four
1149 vldr d24,[sp,#4*(16+0)] @ one
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 145 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
150 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
160 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr",
2539 def : VFP2MnemonicAlias<"flds", "vldr">;
2540 def : VFP2MnemonicAlias<"fldd", "vldr">;
2600 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
2604 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
2684 !if(opc,"vldr","vstr"), !strconcat("\t", sysreg, ", ", Dest), cstr, []>,
|
| D | ARMInstrMVE.td | 5287 defm "": MVE_VLDRSTR_rq_w<MVE_ld, memsz, "vldr" # memsz.MnemonicLetter,
5413 defm "" : MVE_VLDRSTR_qi_m<MVE_ld, memsz, "vldr" # memsz.MnemonicLetter,
5482 "vldr" # memsz.MnemonicLetter # vpt_cond # suffix,
5483 "vldr" # memsz.MnemonicLetter # vpt_cond # memsz.CanonLoadSuffix>;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 726 Mnemonic = "vldr";
730 Mnemonic = "vldr";
9928 "42\005vld43\006vldmdb\006vldmia\004vldr\005vldrb\005vldrd\005vldrh\005v"
12899 …{ 2418 /* vldr */, ARM::VLDR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1M…
12900 …{ 2418 /* vldr */, ARM::VLDR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MM…
12901 …{ 2418 /* vldr */, ARM::VLDR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_…
12902 …{ 2418 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_Has…
12903 …{ 2418 /* vldr */, ARM::VLDR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_Has…
12904 …{ 2418 /* vldr */, ARM::VLDR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMain…
12905 …{ 2418 /* vldr */, ARM::VLDRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_…
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 1638 "llvm.arm.mve.vldr.gather.base",
1639 "llvm.arm.mve.vldr.gather.base.predicated",
1640 "llvm.arm.mve.vldr.gather.base.wb",
1641 "llvm.arm.mve.vldr.gather.base.wb.predicated",
1642 "llvm.arm.mve.vldr.gather.offset",
1643 "llvm.arm.mve.vldr.gather.offset.predicated",
11771 20, // llvm.arm.mve.vldr.gather.base
11772 20, // llvm.arm.mve.vldr.gather.base.predicated
11773 20, // llvm.arm.mve.vldr.gather.base.wb
11774 20, // llvm.arm.mve.vldr.gather.base.wb.predicated
[all …]
|