Searched refs:vop1 (Results 1 – 9 of 9) sorted by relevance
| /third_party/mesa3d/src/amd/compiler/tests/ |
| D | test_sdwa.cpp | 229 writeout(9, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte0_b));
238 writeout(10, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte1_b));
247 writeout(11, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte2_b));
256 writeout(12, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte3_b));
533 Temp val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
539 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
547 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
555 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
565 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]);
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| D | test_assembler.cpp | 53 bld.vop1(aco_opcode::v_nop);
192 bld.vop1(aco_opcode::v_nop);
197 bld.vop1(aco_opcode::v_nop);
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| D | test_insert_nops.cpp | 88 bld.vop1(aco_opcode::v_nop);
147 bld.vop1(aco_opcode::v_nop);
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| D | test_regalloc.cpp | 52 auto result1 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), tmp.def(1).getTemp());
53 auto result2 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), tmp.def(0).getTemp());
73 Temp lo = bld.vop1(aco_opcode::v_not_b32, bld.def(v2b), Operand::zero());
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| D | test_optimizer_postRA.cpp | 390 Temp tmp11_2 = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1, reg_v0), Operand::c32(0));
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| D | test_optimizer.cpp | 860 return bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), val); in emit_denorm_srcdest()
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_lower_to_hw_instr.cpp | 214 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[0]); in emit_int64_dpp_op()
250 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[0]); in emit_int64_dpp_op()
251 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[1], identity[1]); in emit_int64_dpp_op()
274 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[1]); in emit_int64_dpp_op()
279 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[0]); in emit_int64_dpp_op()
285 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[0]); in emit_int64_dpp_op()
291 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[0]); in emit_int64_dpp_op()
313 bld.vop1(aco_opcode::v_mov_b32, Definition(vtmp, v1), src0[0]); in emit_int64_op()
314 bld.vop1(aco_opcode::v_mov_b32, Definition(PhysReg{vtmp + 1}, v1), src0[1]); in emit_int64_op()
321 bld.vop1(aco_opcode::v_mov_b32, Definition(PhysReg{vtmp + 1}, v1), src0[1]); in emit_int64_op()
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| D | aco_instruction_selection.cpp | 973 bld.vop1(op, bld.def(RegType::vgpr, dst.size()), get_alu_src(ctx, instr->src[0]))); in emit_vop1_instruction()
975 bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0])); in emit_vop1_instruction()
1156 scaled = bld.vop1(op, bld.def(v1), scaled); in emit_scaled_op()
1159 Temp not_scaled = bld.vop1(op, bld.def(v1), val); in emit_scaled_op()
1168 bld.vop1(aco_opcode::v_rcp_f32, dst, val); in emit_rcp()
1179 bld.vop1(aco_opcode::v_rsq_f32, dst, val); in emit_rsq()
1190 bld.vop1(aco_opcode::v_sqrt_f32, dst, val); in emit_sqrt()
1201 bld.vop1(aco_opcode::v_log_f32, dst, val); in emit_log2()
1212 return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val); in emit_trunc_f64()
1238 Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo); in emit_trunc_f64()
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| D | aco_ir.h | 1230 VOP1_instruction& vop1() noexcept in vop1() function
1235 const VOP1_instruction& vop1() const noexcept in vop1() function
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