Searched refs:vzip (Results 1 – 20 of 20) sorted by relevance
74 …vzip.8 d6, d10 @ d6 = R1R2R3R4R5R6R7R8 d10 = R…75 …vzip.8 d7, d11 @ d7 = G1G2G3G4G5G6G7G8 d11 = G…76 …vzip.8 d8, d12 @ d8 = B1B2B3B4B5B6B7B8 d12 = B…77 …vzip.8 d9, d13 @ d9 = A1A2A3A4A5A6A7A8 d13 = A…
52 …vzip.16 q7, q8 @ A,I,B,J,C,K,D,L,E,M,F,N,G,O,H…
133 vzip.u8 reg1, reg3134 vzip.u8 reg2, reg4135 vzip.u8 reg3, reg4136 vzip.u8 reg1, reg2165 vzip.u8 xreg1, xreg3167 vzip.u8 xreg2, xreg4169 vzip.u8 xreg3, xreg4171 vzip.u8 xreg1, xreg2174 vzip.u8 yreg1, yreg3176 vzip.u8 yreg2, yreg4[all …]
2892 vzip.u8 reg1, reg32893 vzip.u8 reg2, reg42894 vzip.u8 reg3, reg42895 vzip.u8 reg1, reg22924 vzip.u8 xreg1, xreg32926 vzip.u8 xreg2, xreg42928 vzip.u8 xreg3, xreg42930 vzip.u8 xreg1, xreg22933 vzip.u8 yreg1, yreg32935 vzip.u8 yreg2, yreg4[all …]
344 vzip.8 d®1, d®21183 vzip.u16 out0, out1 /* everything is in place */
167 vzip.32 d18, d22170 vzip.32 d19, d23176 vzip.32 d2, d6178 vzip.32 d3, d7
165 vzip.32 d18, d22168 vzip.32 d19, d23174 vzip.32 d2, d6176 vzip.32 d3, d7
129 vzip.32 q10, q11166 vzip.32 q12, q14188 vzip.32 q13, q15231 vzip.32 q10, q11263 vzip.32 q10, q11
754 vzip.8 d0, d1755 vzip.8 d0, d1810 vzip.32 q0, q2811 vzip.32 q1, q3812 vzip.32 q0, q1813 vzip.32 q2, q3
227 vzip.s16 d0, d2 // uinc -uinc uinc -uinc274 vzip.32 d28, d29 //q14: 000d000c000b000a;
321 vzip.16 q1, q4
386 vzip.8 d2, d1
432 vzip.8 d2, d1
549 void vzip(Type ElmtTy, const Operand *OpQd, const Operand *OpQn,
1247 Asm->vzip(typeElementType(DestTy), Dest, Src0, Src1); in emitIAS()
3466 void AssemblerARM32::vzip(Type ElmtTy, const Operand *OpQd, const Operand *OpQn, in vzip() function in Ice::ARM32::AssemblerARM32
2364 vzip.8 d10, d112365 vzip.8 d12, d13
6989 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;6990 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;6991 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.6992 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",6995 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;6996 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;6997 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;8904 def : NEONMnemonicAlias<"vzipq", "vzip">;
1198 Mnemonic = "vzip";9957 "bw\004vswp\004vtbl\004vtbx\004vtrn\004vtst\005vudot\004vuzp\004vzip\003"15076 …{ 3929 /* vzip */, ARM::VZIPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_H…15077 …{ 3929 /* vzip */, ARM::VZIPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_H…15078 …{ 3929 /* vzip */, ARM::VZIPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_H…15079 …{ 3929 /* vzip */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_H…15080 …{ 3929 /* vzip */, ARM::VZIPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_Ha…15081 …{ 3929 /* vzip */, ARM::VZIPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_Ha…