Searched refs:HDMI_ACR_PACKET_CONTROL (Results 1 – 12 of 12) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_stream_encoder.h | 76 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
178 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
179 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
180 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
679 uint32_t HDMI_ACR_PACKET_CONTROL; member
|
| D | dce_stream_encoder.c | 1383 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, in dce110_se_setup_hdmi_audio()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | evergreen_hdmi.c | 80 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
83 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
|
| D | rv770d.h | 693 #define HDMI_ACR_PACKET_CONTROL 0x740c macro
|
| D | evergreend.h | 538 #define HDMI_ACR_PACKET_CONTROL 0x703c macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_stream_encoder.h | 66 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
150 uint32_t HDMI_ACR_PACKET_CONTROL; member
|
| D | dcn10_stream_encoder.c | 1314 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, in enc1_se_setup_hdmi_audio()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dio_stream_encoder.h | 69 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
|
| D | dcn30_dio_stream_encoder.c | 730 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, in enc3_se_setup_hdmi_audio()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v10_0.c | 1674 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); in dce_v10_0_afmt_setmode()
1677 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); in dce_v10_0_afmt_setmode()
1679 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v10_0_afmt_setmode()
|
| D | dce_v11_0.c | 1716 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); in dce_v11_0_afmt_setmode()
1719 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); in dce_v11_0_afmt_setmode()
1721 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v11_0_afmt_setmode()
|
| D | dce_v6_0.c | 1418 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v6_0_audio_set_acr()
1419 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, in dce_v6_0_audio_set_acr()
|