// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
 * Copyright (C) 2020 frank@allwinnertech.com
 */

#include <dt-bindings/clock/sun50iw9-ccu.h>
#include <dt-bindings/clock/sun50iw9-ccu-rtc.h>
#include <dt-bindings/clock/sun50iw9-r-ccu.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/sun4i-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50iw9-ccu.h>
#include <dt-bindings/reset/sun50iw9-r-ccu.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&wakeupgen>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases: aliases  {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		pwm = &pwm;
		pwm0 = &pwm0;
		pwm1 = &pwm1;
		pwm2 = &pwm2;
		pwm3 = &pwm3;
		pwm4 = &pwm4;
		pwm5 = &pwm5;
		ir0 = &s_cir0;
		/*mmc0 = &sdc0;
		mmc2 = &sdc2;*/
		sunxi-mmc0 = &sdc0;
		sunxi-mmc2 = &sdc2;
		tv0 = &tv0;
		gmac0 = &gmac0;
		ac200 = &ac200;
		nand0 = &nand0;
		ve0 = &ve;
		ve1 = &ve1;
		drm = &drm;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		bl31 {
			reg = <0x0 0x48000000 0x0 0x01000000>;
		};
	};

	firmware {
		android {
			compatible = "android,firmware";
			name = "android";
			boot_devices = "soc@3000000/4020000.sdmmc,soc@3000000/4022000.sdmmc,soc@3000000";
			vbmeta {
				compatible = "android,vbmeta";
				parts = "vbmeta,vbmeta_system,vbmeta_vendor,boot";
			};
		};
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&ccu CLK_CPUX>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP>;
			dynamic-power-coefficient = <202>;
			#cooling-cells = <2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			clocks = <&ccu CLK_CPUX>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP>;
			dynamic-power-coefficient = <202>;
			#cooling-cells = <2>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			enable-method = "psci";
			clocks = <&ccu CLK_CPUX>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP>;
			dynamic-power-coefficient = <202>;
			#cooling-cells = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			enable-method = "psci";
			clocks = <&ccu CLK_CPUX>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP>;
			dynamic-power-coefficient = <202>;
			#cooling-cells = <2>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <46>;
				exit-latency-us = <59>;
				min-residency-us = <3570>;
			};
		};
	};

	cpu_opp_table: cpu-opp-table {
		compatible = "allwinner,sun50i-operating-points";
		nvmem-cells = <&speedbin_efuse>;
		nvmem-cell-names = "speed";
		opp-shared;

		opp@480000000 {
			opp-hz = /bits/ 64 <480000000>;
			opp-microvolt-a0 = <900000>;
			opp-microvolt-a1 = <900000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x11>;
		};

		opp@600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt-a1 = <900000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x1>;
		};

		opp@720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt-a0 = <900000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x10>;
		};

		opp@792000000 {
			opp-hz = /bits/ 64 <792000000>;
			opp-microvolt-a1 = <900000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x1>;
		};

		opp@936000000 {
			opp-hz = /bits/ 64 <936000000>;
			opp-microvolt-a0 = <900000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x10>;
		};

		opp@1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt-a0 = <950000>;
			opp-microvolt-a1 = <900000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x11>;
		};

		opp@1104000000 {
			opp-hz = /bits/ 64 <1104000000>;
			opp-microvolt-a0 = <1000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x10>;
		};

		opp@1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt-a0 = <1050000>;
			opp-microvolt-a1 = <960000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x11>;
		};

		opp@1320000000 {
			opp-hz = /bits/ 64 <1320000000>;
			opp-microvolt-a0 = <1100000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x10>;
		};

		opp@1416000000 {
			opp-hz = /bits/ 64 <1416000000>;
			opp-microvolt-a0 = <1150000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x10>;
		};

		opp@1512000000 {
			opp-hz = /bits/ 64 <1512000000>;
			opp-microvolt-a1 = <1100000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-supported-hw = <0x1>;
		};
	};

	dump_reg: dump-reg@20000 {
		compatible = "allwinner,sunxi-dump-reg";
		reg = <0x0 0x00020000 0x0 0x0004>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	iosc: internal-osc-clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <16000000>;
		clock-accuracy = <300000000>;
		clock-output-names = "iosc";
	};

	dcxo24M: dcxo24M-clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "dcxo24M";
	};

	osc32k: osc32k-clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "osc32k";
	};

	gic: interrupt-controller@3021000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
		      <0x0 0x03022000 0 0x2000>, /* GIC CPU */
		      <0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
		      <0x0 0x03026000 0 0x2000>; /* GIC VCPU */
		interrupts = <GIC_PPI 9 0xf04>;  /* GIC Maintenence IRQ */
		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@0 {
		compatible = "allwinner,sunxi-wakeupgen";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
	};

	timer_arch {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			   <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			   <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			   <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
		interrupt-parent = <&gic>;
		arm,no-tick-in-suspend;
	};

	reg_pio1_8: pio-18 {
		compatible = "regulator-fixed";
		regulator-name = "pio-18";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_pio3_3: pio-33 {
		compatible = "regulator-fixed";
		regulator-name = "pio-33";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	soc: soc@3000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		vind0:vind@6600800 {
			compatible = "allwinner,sunxi-vin-media", "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			device_id = <0>;
			csi_top = <324000000>;
			reg = <0x0 0x06600800 0x0 0x200>,
				<0x0 0x06600000 0x0 0x800>;
			clocks = <&ccu CLK_CSI_TOP>, <&ccu CLK_PLL_CSI>,
				 <&ccu CLK_CSI0_MCLK>, <&dcxo24M>, <&ccu CLK_PLL_CSI>,
				 <&ccu CLK_CSI1_MCLK>, <&dcxo24M>, <&ccu CLK_PLL_CSI>,
				 <&ccu CLK_BUS_CSI>, <&ccu CLK_MBUS_CSI>;
			clock-names = "csi_top", "csi_top_src",
					"csi_mclk0", "csi_mclk0_24m", "csi_mclk0_pll",
					"csi_mclk1", "csi_mclk1_24m", "csi_mclk1_pll",
					"csi_bus", "csi_mbus";
			resets = <&ccu RST_BUS_CSI>;
			reset-names = "csi_ret";
			pinctrl-names = "mclk0-default","mclk0-sleep","mclk1-default","mclk1-sleep";
			pinctrl-0 = <&csi_mclk0_pins_a>;
			pinctrl-1 = <&csi_mclk0_pins_b>;
			pinctrl-2 = <&csi_mclk1_pins_a>;
			pinctrl-3 = <&csi_mclk1_pins_b>;
			status = "okay";

			csi_cci0:cci@6614000 {
				compatible = "allwinner,sunxi-csi_cci";
				reg = <0x0 0x06614000 0x0 0x400>;
				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default","sleep";
				pinctrl-0 = <&csi_cci0_pins_a>;
				pinctrl-1 = <&csi_cci0_pins_b>;
				device_id = <0>;
				status = "okay";
			};
			csi_cci1:cci@6614400 {
				compatible = "allwinner,sunxi-csi_cci";
				reg = <0x0 0x06614400 0x0 0x400>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default","sleep";
				pinctrl-0 = <&csi_cci1_pins_a>;
				pinctrl-1 = <&csi_cci1_pins_b>;
				device_id = <1>;
				status = "okay";
			};
			csi0:csi@6601000 {
				device_type = "csi0";
				compatible = "allwinner,sunxi-csi";
				reg = <0x0 0x06601000 0x0 0x1000>;
				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				device_id = <0>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			csi1:csi@6602000 {
				device_type = "csi1";
				compatible = "allwinner,sunxi-csi";
				reg = <0x0 0x06602000 0x0 0x1000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default","sleep";
				pinctrl-0 = <&csi1_pins_a>;
				pinctrl-1 = <&csi1_pins_b>;
				device_id = <1>;
				iommus = <&mmu_aw 4 1>;
				status = "disabled";
			};
			mipi0:mipi@660c000 {
				compatible = "allwinner,sunxi-mipi";
				reg = <0x0 0x0660C000 0x0 0x1000>;
				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
				device_id = <0>;
				status = "okay";
			};
			isp0:isp@6614810 {
				compatible = "allwinner,sunxi-isp";
				reg = <0x0 0x06614810 0x0 0x10>;
				device_id = <0xfe>;
				status = "okay";
			};
			isp1:isp@6614820 {
				compatible = "allwinner,sunxi-isp";
				reg = <0x0 0x06614820 0x0 0x10>;
				device_id = <0xff>;
				status = "okay";
			};
			scaler0:scaler@6614830 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x06614830 0x0 0x10>;
				device_id = <0xfa>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler1:scaler@6614840 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x06614840 0x0 0x10>;
				device_id = <0xfb>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler2:scaler@6614850 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x06614850 0x0 0x10>;
				device_id = <0xfc>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler3:scaler@6614860 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x06614860 0x0 0x10>;
				device_id = <0xfd>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler4:scaler@6614870 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x06614870 0x0 0x10>;
				device_id = <0xfe>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler5:scaler@6614880 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x06614880 0x0 0x10>;
				device_id = <0xff>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			actuator0:actuator@6614890 {
				reg = <0x0 0x06614890 0x0 0x10>;
				device_type = "actuator0";
				compatible = "allwinner,sunxi-actuator";
				actuator0_name = "ad5820_act";
				actuator0_slave = <0x18>;
				actuator0_af_pwdn = <>;
				actuator0_afvdd = "afvcc-csi";
				actuator0_afvdd_vol = <2800000>;
				status = "disabled";
			};
			flash0:flash@66148a0 {
				reg = <0x0 0x066148a0 0x0 0x10>;
				device_type = "flash0";
				compatible = "allwinner,sunxi-flash";
				flash0_type = <2>;
				flash0_en = <>;
				flash0_mode = <>;
				flash0_flvdd = "";
				flash0_flvdd_vol = <>;
				device_id = <0>;
				status = "disabled";
			};
			sensor0:sensor@66148b0 {
				reg = <0x0 0x066148b0 0x0 0x10>;
				device_type = "sensor0";
				compatible = "allwinner,sunxi-sensor";
				sensor0_mname = "rn6854m_mipi";
				sensor0_twi_cci_id = <0>;
				sensor0_twi_addr = <0x58>;
				sensor0_mclk_id = <0>;
				sensor0_pos = "rear";
				sensor0_isp_used = <0>;
				sensor0_fmt = <0>;
				sensor0_stby_mode = <0>;
				sensor0_vflip = <0>;
				sensor0_hflip = <0>;
				sensor0_cameravdd-supply = <>;
				sensor0_cameravdd_vol = <>;
				sensor0_reservevdd-supply = <>;
				sensor0_reservevdd_vol = <>;
				sensor0_iovdd-supply = <>;
				sensor0_iovdd_vol = <>;
				sensor0_avdd-supply = <>;
				sensor0_avdd_vol = <>;
				sensor0_dvdd-supply = <>;
				sensor0_dvdd_vol = <>;
				sensor0_power_en = <>;
				sensor0_reset = <&pio PI 13 GPIO_ACTIVE_LOW>;
				sensor0_pwdn = <&pio PI 14 GPIO_ACTIVE_LOW>;
				sensor0_sm_vs = <>;
				flash_handle = <&flash0>;
				act_handle = <&actuator0>;
				device_id = <0>;
				status	= "okay";
			};
			sensor1:sensor@66148c0 {
				reg = <0x0 0x066148c0 0x0 0x10>;
				device_type = "sensor1";
				compatible = "allwinner,sunxi-sensor";
				sensor1_mname = "nvp6158";
				sensor1_twi_cci_id = <1>;
				sensor1_twi_addr = <0x64>;
				sensor1_mclk_id = <1>;
				sensor1_pos = "front";
				sensor1_isp_used = <0>;
				sensor1_fmt = <0>;
				sensor1_stby_mode = <0>;
				sensor1_vflip = <0>;
				sensor1_hflip = <0>;
				sensor1_cameravdd-supply = <>;
				sensor1_cameravdd_vol = <>;
				sensor1_reservevdd-supply = <>;
				sensor1_reservevdd_vol = <>;
				sensor1_iovdd-supply = <>;
				sensor1_iovdd_vol = <>;
				sensor1_avdd-supply = <>;
				sensor1_avdd_vol = <>;
				sensor1_dvdd-supply = <>;
				sensor1_dvdd_vol = <>;
				sensor1_power_en = <>;
				sensor1_reset = <&pio PI 12 GPIO_ACTIVE_LOW>;
				sensor1_pwdn = <&pio PI 14 GPIO_ACTIVE_LOW>;
				sensor1_sm_vs = <>;
				flash_handle = <>;
				act_handle = <>;
				device_id = <1>;
				status	= "okay";
			};
			vinc0:vinc@6609000 {
				device_type = "vinc0";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609000 0x0 0x200>;
				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				vinc0_csi_sel = <0>;
				vinc0_mipi_sel = <0>;
				vinc0_isp_sel = <0>;
				vinc0_isp_tx_ch = <0>;
				vinc0_rear_sensor_sel = <0>;
				vinc0_front_sensor_sel = <0>;
				vinc0_sensor_list = <0>;
				device_id = <0>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			vinc1:vinc@6609200 {
				device_type = "vinc1";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609200 0x0 0x200>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
				vinc1_csi_sel = <0>;
				vinc1_mipi_sel = <0>;
				vinc1_isp_sel = <0>;
				vinc1_isp_tx_ch = <1>;
				vinc1_rear_sensor_sel = <0>;
				vinc1_front_sensor_sel = <0>;
				vinc1_sensor_list = <0>;
				device_id = <1>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			vinc2:vinc@6609400 {
				device_type = "vinc2";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609400 0x0 0x200>;
				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				vinc2_csi_sel = <1>;
				vinc2_mipi_sel = <0xff>;
				vinc2_isp_sel = <1>;
				vinc2_isp_tx_ch = <0>;
				vinc2_rear_sensor_sel = <1>;
				vinc2_front_sensor_sel = <1>;
				vinc2_sensor_list = <0>;
				device_id = <2>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			vinc3:vinc@6609600 {
				device_type = "vinc3";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609600 0x0 0x200>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
				vinc3_csi_sel = <1>;
				vinc3_mipi_sel = <0xff>;
				vinc3_isp_sel = <1>;
				vinc3_isp_tx_ch = <1>;
				vinc3_rear_sensor_sel = <1>;
				vinc3_front_sensor_sel = <1>;
				vinc3_sensor_list = <0>;
				device_id = <3>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			vinc4:vinc@6609800 {
				device_type = "vinc4";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609800 0x0 0x200>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				vinc4_csi_sel = <1>;
				vinc4_mipi_sel = <0xff>;
				vinc4_isp_sel = <1>;
				vinc4_isp_tx_ch = <2>;
				vinc4_rear_sensor_sel = <1>;
				vinc4_front_sensor_sel = <1>;
				vinc4_sensor_list = <0>;
				device_id = <4>;
				iommus = <&mmu_aw 5 1>;
				status = "okay";
			};
			vinc5:vinc@6609A00 {
				device_type = "vinc5";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x06609A00 0x0 0x200>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				vinc5_csi_sel = <1>;
				vinc5_mipi_sel = <0xff>;
				vinc5_isp_sel = <1>;
				vinc5_isp_tx_ch = <3>;
				vinc5_rear_sensor_sel = <1>;
				vinc5_front_sensor_sel = <1>;
				vinc5_sensor_list = <0>;
				device_id = <5>;
				iommus = <&mmu_aw 5 1>;
				status = "okay";
			};
		};

		disp: disp@1000000 {
			compatible = "allwinner,sunxi-disp";
			reg = <0x0 0x01000000 0x0 0x01400000>, /*de*/
			      <0x0 0x06510000 0x0 0x200>, /* display_if_top */
			      <0x0 0x06511000 0x0 0x1000>, /* tcon_lcd0 */
			      <0x0 0x06512000 0x0 0x1000>, /* tcon_lcd1 */
			      <0x0 0x06515000 0x0 0x1000>, /* tcon_tv0 */
			      <0x0 0x06516000 0x0 0x1000>; /* tcon_tv1 */
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* DE */
				     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd0 */
				     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd1 */
				     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, /* tcon_tv0 */
				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* tcon_tv1 */
			clocks = <&ccu CLK_DE>,
				 <&ccu CLK_DE>,
				 <&ccu CLK_BUS_DE>,
				 <&ccu CLK_BUS_DE>,
				 <&ccu CLK_TCON_LCD0>,
				 <&ccu CLK_TCON_LCD1>,
				 <&ccu CLK_TCON_TV0>,
				 <&ccu CLK_TCON_TV1>,
				 <&ccu CLK_BUS_TCON_LCD0>,
				 <&ccu CLK_BUS_TCON_LCD1>,
				 <&ccu CLK_BUS_TCON_TV0>,
				 <&ccu CLK_BUS_TCON_TV1>,
				 <&ccu CLK_BUS_DISPLAY_IF_TOP>,
				 <&ccu CLK_BUS_DISPLAY_IF_TOP>,
				 <&ccu CLK_BUS_DISPLAY_IF_TOP>,
				 <&ccu CLK_BUS_DISPLAY_IF_TOP>;
			clock-names = 	"clk_de0",
					"clk_de1",
					"clk_bus_de0",
					"clk_bus_de1",
					"clk_tcon0", /* tcon lcd */
					"clk_tcon1",
					"clk_tcon2", /* tcon tv */
					"clk_tcon3",
					"clk_bus_tcon0",
					"clk_bus_tcon1",
					"clk_bus_tcon2",
					"clk_bus_tcon3",
					"clk_bus_dpss_top0",
					"clk_bus_dpss_top1",
					"clk_bus_dpss_top2",
					"clk_bus_dpss_top3";
			resets = <&ccu RST_BUS_DE>,
				 <&ccu RST_BUS_DE>,
				 <&ccu RST_BUS_TCON_LCD0>,
				 <&ccu RST_BUS_TCON_LCD1>,
				 <&ccu RST_BUS_TCON_TV0>,
				 <&ccu RST_BUS_TCON_TV1>,
				 <&ccu RST_BUS_LVDS>,
				 <&ccu RST_BUS_LVDS>,
				 <&ccu RST_BUS_DISPLAY_IF_TOP>,
				 <&ccu RST_BUS_DISPLAY_IF_TOP>,
				 <&ccu RST_BUS_DISPLAY_IF_TOP>,
				 <&ccu RST_BUS_DISPLAY_IF_TOP>;
			reset-names = 	"rst_bus_de0",
					"rst_bus_de1",
					"rst_bus_tcon0",
					"rst_bus_tcon1",
					"rst_bus_tcon2",
					"rst_bus_tcon3",
					"rst_bus_lvds0",
					"rst_bus_lvds1",
					"rst_bus_dpss_top0",
					"rst_bus_dpss_top1",
					"rst_bus_dpss_top2",
					"rst_bus_dpss_top3";
			assigned-clocks = <&ccu CLK_TCON_TV0>;
			assigned-clock-parents = <&ccu CLK_PLL_VIDEO2>;
			assigned-clock-rates = <0>;
			iommus = <&mmu_aw 0 0>;

			boot_disp = <0>;
			fb_base = <0>;
		};

		drm: drm@01000000 {
			compatible = "allwinner,sunxi-drm";
			fb_base = <0>;
			iommus = <&mmu_aw 0 0>; /* 1：enable iommu */
			status = "okay";
		};

		drm_de: de@01000000 {
			compatible = "allwinner,sunxi-de";
			reg = <0x0 0x01000000 0x0 0x01400000>;/*de*/
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; /*DE*/
			clocks = <&ccu CLK_DE>,
					<&ccu CLK_BUS_DE>;
			clock-names = "clk_de","clk_bus_de";
			resets = <&ccu RST_BUS_DE>;
			reset-names = "rst_bus_de";
			chn_cfg_mode = <1>;
			status = "okay";
		};

		drm_tcon: tcon@06511000 {
			compatible = "allwinner,sunxi-tcon";
			reg = <0x0 0x06510000 0x0 0x200>,/*disp_if_top*/
			<0x0 0x06511000 0x0 0x1000>,/*tcon_lcd0*/
			<0x0 0x06512000 0x0 0x1000>,/*tcon_lcd1*/
			<0x0 0x06515000 0x0 0x1000>,/*tcon_tv0*/
			<0x0 0x06516000 0x0 0x1000>;/*tcon_tv1*/
			interrupts =
			<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /*tcon_lcd0*/
			<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /*tcon_lcd1*/
			<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, /*tcon_tv0*/
			<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /*tcon_tv1*/
			clocks = <&ccu CLK_BUS_DISPLAY_IF_TOP>,
				 <&ccu CLK_TCON_LCD0>,
				 <&ccu CLK_TCON_LCD1>,
				 <&ccu CLK_TCON_TV0>,
				 <&ccu CLK_TCON_TV1>,
				 <&ccu CLK_BUS_TCON_LCD0>,
				 <&ccu CLK_BUS_TCON_LCD1>,
				 <&ccu CLK_BUS_TCON_TV0>,
				 <&ccu CLK_BUS_TCON_TV1>;
			clock-names = "clk_bus_dpss_top0",
						"clk_tcon0", /* tcon lcd */
						"clk_tcon1",
						"clk_tcon2", /* tcon tv */
						"clk_tcon3",
						"clk_bus_tcon0",
						"clk_bus_tcon1",
						"clk_bus_tcon2",
						"clk_bus_tcon3";
			resets = <&ccu RST_BUS_DISPLAY_IF_TOP>,
					<&ccu RST_BUS_TCON_LCD0>,
					<&ccu RST_BUS_TCON_LCD1>,
					<&ccu RST_BUS_TCON_TV0>,
					<&ccu RST_BUS_TCON_TV1>;
			reset-names = "rst_bus_dpss_top",
						"rst_bus_tcon0",
						"rst_bus_tcon1",
						"rst_bus_tcon2",
						"rst_bus_tcon3";
			status = "okay";
		};

		lcdcore: lcd-core@01c0c000 {
			compatible = "allwinner,sunxi-lcd";
			resets = <&ccu RST_BUS_LVDS>;
			reset-names = "rst_bus_lvds";
			status = "okay";
		};

		ve: ve@1c0e000 {
			compatible = "allwinner,sunxi-cedar-ve";
			reg = <0x0 0x01c0e000 0x0 0x1000>,
			      <0x0 0x03000000 0x0 0x10>,
			      <0x0 0x03001000 0x0 0x1000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, <&ccu CLK_MBUS_VE>;
			clock-names = "bus_ve", "ve", "mbus_ve";
			resets = <&ccu RST_BUS_VE>;
			iommus = <&mmu_aw 3 1>;
		};

		ve1: ve1@1c0e000 {
			compatible = "allwinner,sunxi-cedar-ve";
			iommus = <&mmu_aw 2 1>;
		};


		g2d: g2d@1480000 {
			compatible = "allwinner,sunxi-g2d";
			reg = <0x0 0x01480000 0x0 0x3ffff>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_G2D>, <&ccu CLK_G2D>,
				 <&ccu CLK_MBUS_G2D>;
			clock-names = "bus", "g2d", "mbus_g2d";
			resets = <&ccu RST_BUS_G2D>;
			iommus = <&mmu_aw 6 1>;
		};

		di:deinterlace@1420000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sunxi-deinterlace";
			reg = <0x0 0x01420000 0x0 0x040000>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			iommus = <&mmu_aw 1 1>;
			status = "okay";

			clocks = <&ccu CLK_DI>,
				 <&ccu CLK_BUS_DI>,
				 <&ccu CLK_PLL_PERIPH0_2X>;
			clock-names = "clk_di",
				      "clk_bus_di",
				      "pll_periph";
			resets = <&ccu RST_BUS_DI>;
			reset-names = "rst_bus_di";

			assigned-clocks = <&ccu CLK_DI>;
			assigned-clock-parents = <&ccu CLK_PLL_PERIPH0_2X>;
			assigned-clock-rates = <300000000>;
		};

		gpu: gpu@1800000 {
			device_type = "gpu";
			compatible = "arm,mali-bifrost";
			reg = <0x0 0x01800000 0x0 0x10000>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "job", "mmu", "gpu";
			clocks = <&ccu CLK_PLL_GPU>, <&ccu CLK_GPU0>,
				 <&ccu CLK_GPU1>,<&ccu CLK_BUS_GPU>;
			clock-names = "clk_parent", "clk_mali",
				      "clk_bak", "clk_bus";
			resets = <&ccu RST_BUS_GPU>;
			reset-names = "rst_bus_gpu";
			#cooling-cells = <2>;
			operating-points-v2 = <&gpu_opp_table>;
			mali-supply = <&reg_dcdc4>;
			ipa_dvfs:ipa_dvfs {
				compatible = "arm,mali-simple-power-model";
				static-coefficient = <17000>;
				dynamic-coefficient = <750>;
				ts = <254682 9576 0xffffff98 4>;
				thermal-zone = "gpu_thermal_zone";
				ss-coefficient = <36>;
				ff-coefficient = <291>;
			};
		};

		gpu_opp_table: gpu-opp-table {
			compatible = "operating-points-v2";

			opp-420000000 {
				opp-hz = /bits/ 64 <420000000>;
				opp-microvolt = <820000>;
			};
			opp-456000000 {
				opp-hz = /bits/ 64 <456000000>;
				opp-microvolt = <840000>;
			};
			opp-504000000 {
				opp-hz = /bits/ 64 <504000000>;
				opp-microvolt = <860000>;
			};
			opp-552000000 {
				opp-hz = /bits/ 64 <552000000>;
				opp-microvolt = <880000>;
			};
			opp-600000000 {
				opp-hz = /bits/ 64 <600000000>;
				opp-microvolt = <900000>;
			};
			opp-648000000 {
				opp-hz = /bits/ 64 <648000000>;
				opp-microvolt = <960000>;
			};
		};

		lcd0: lcd0@1c0c000 {
			compatible = "allwinner,sunxi-lcd0";
			/* Fake registers to avoid dtc compiling warnings */
			reg = <0x0 0x1c0c000 0x0 0x0>;
			pinctrl-names = "active","sleep";
		};

		tv0: tv0@6520000 {
			compatible = "allwinner,sunxi-tv";
			reg = <0x0 0x06520000 0x0 0x100>,
				<0x0 0x06524000 0x0 0x3fc>;
			clocks = <&ccu CLK_BUS_TVE_TOP>,
				 <&ccu CLK_TVE>,
				 <&ccu CLK_BUS_TVE>;
			clock-names = "clk_bus_tve_top",
				      "clk_tve",
				      "clk_bus_tve";
			resets = <&ccu RST_BUS_TVE_TOP>,
				 <&ccu RST_BUS_TVE>;
			reset-names = "rst_bus_tve_top", "rst_bus_tve";

			assigned-clocks = <&ccu CLK_TVE>;
			assigned-clock-parents = <&ccu CLK_PLL_VIDEO1>;
			nvmem-cells = <&tvout>;
			nvmem-cell-names = "tvout";

			device_type = "tv0";
			pinctrl-names = "active","sleep";
			status = "okay";
		};

		ccu: ccu@3001000 {
			compatible = "allwinner,sun50iw9-ccu";
			reg = <0x0 0x03001000 0x0 0x1000>;
			clocks = <&dcxo24M>, <&osc32k>, <&iosc>;
			clock-names = "hosc", "losc", "iosc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		rtc_ccu: rtc_ccu@7000000 {
			compatible = "allwinner,sun50iw9-rtc-ccu";
			reg = <0x0 0x07000000 0x0 0x400>;
			#clock-cells = <1>;
			clocks = <&osc32k>;
			clock-names = "losc";
			#reset-cells = <1>;
		};

		rtc: rtc@7000000 {
			compatible = "allwinner,rtc-v200";
			device_type = "rtc";
			wakeup-source;
			reg = <0x0 0x07000000 0x0 0x200>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_AHB_BUS_RTC>, <&rtc_ccu CLK_RTC_1K>;
			clock-names = "r-ahb-rtc","rtc-1k";
			gpr_cur_pos = <6>;
		};

		r_ccu: r_ccu@7010000 {
			compatible = "allwinner,sun50iw9-r-ccu";
			reg = <0x0 0x07010000 0x0 0x300>;
			/* have no irq line */
			clocks = <&dcxo24M>, <&osc32k>, <&iosc>,
				 <&ccu CLK_PLL_PERIPH0>;
			clock-names = "hosc", "losc", "iosc", "pll-periph";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		dma: dma-controller@3002000 {
			compatible = "allwinner,sun50iw9-dma";
			reg = <0x0 0x03002000 0x0 0x1000>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
			clock-names = "bus", "mbus";
			dma-channels = <16>;
			dma-requests = <49>;
			resets = <&ccu RST_BUS_DMA>;
			#dma-cells = <1>;
		};

		sram_ctrl: sram_ctrl@3000000 {
			compatible = "allwinner,sram_ctrl";
			reg = <0x0 0x3000000 0 0x16C>;
			soc_ver {
				offset = <0x24>;
				mask = <0x7>;
				shift = <0>;
			};

			soc_id {
				offset = <0x200>;
				mask = <0x1>;
				shift = <22>;
			};

			soc_bin {
				offset = <0x0>;
				mask = <0x3ff>;
				shift = <0x0>;
			};

		};

		sid@3006000 {
			compatible = "allwinner,sun50iw9p1-sid", "allwinner,sunxi-sid";
			reg = <0x0 0x03006000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			speedbin_efuse: speed@00 {
				reg = <0x0 2>;
			};

			ths_calib: calib@14 {
				reg = <0x14 8>;
			};

			tvout: tvout@2e {
				reg = <0x2c 8>;
			};

			i_cpu_efuse: i-cpu@28 {
				reg = <0x28 2>;
			};

			/* some guys has nothing to do with nvmem */
			secure_status {
				reg = <0x0 0>;
				offset = <0xa0>;
				size = <0x4>;
			};

			chipid {
				reg = <0x0 0>;
				offset = <0x200>;
				size = <0x10>;
			};

			rotpk {
				reg = <0x0 0>;
				offset = <0x270>;
				size = <0x20>;
			};
		};

		cryptoengine: ce@1904000 {
			compatible = "allwinner,sunxi-ce";
			device_name = "ce";
			reg = <0x0 0x01904000 0x0 0xa0>, /* non-secure space */
			      <0x0 0x01904800 0x0 0xa0>; /* secure space */
			interrupts = <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, /*non-secure*/
				   <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>; /* secure*/
			clock-frequency = <300000000>; /* 300MHz */
			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>,
					<&ccu CLK_PLL_PERIPH0_2X>;
			clock-names = "bus_ce", "ce_clk", "mbus_ce", "pll_periph0_2x";
			resets = <&ccu RST_BUS_CE>;
		};

		soc_timer0: timer@3009000 {
			compatible = "allwinner,sun4i-a10-timer";
			device_type = "soc_timer";
			/*
			 * FIXME: After using sunxi timer driver, the number
			 * of CPU entering idle becomes less?
			 * "allwinner,sunxi-timer";
			 */
			reg = <0x0 0x03009000 0x0 0x400>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>;
		};

		wdt: watchdog@30090a0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x0 0x030090a0 0x0 0x20>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
		};

		pwm: pwm@300a000 {
			compatible = "allwinner,sunxi-pwm-v100";
			reg = <0x0 0x0300a000 0x0 0x400>;
			clocks = <&ccu CLK_BUS_PWM>;
			resets = <&ccu RST_BUS_PWM>;
			pwm-number = <6>;
			pwm-base = <0>;
			sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>,
				<&pwm4>, <&pwm5>;
		};

		pwm0: pwm0@300a010 {
			compatible = "allwinner,sunxi-pwm0";
			reg = <0x0 0x0300a010 0x0 0x4>;
			reg_base = <0x0300a000>;
		};

		pwm1: pwm1@300a011 {
			compatible = "allwinner,sunxi-pwm1";
			reg = <0x0 0x0300a011 0x0 0x4>;
			reg_base = <0x0300a000>;
		};

		pwm2: pwm2@300a012 {
			compatible = "allwinner,sunxi-pwm2";
			reg = <0x0 0x0300a012 0x0 0x4>;
			reg_base = <0x0300a000>;
		};

		pwm3: pwm3@300a013 {
			compatible = "allwinner,sunxi-pwm3";
			reg = <0x0 0x0300a013 0x0 0x4>;
			reg_base = <0x0300a000>;
		};

		pwm4: pwm4@300a014 {
			compatible = "allwinner,sunxi-pwm4";
			reg = <0x0 0x0300a014 0x0 0x4>;
			reg_base = <0x0300a000>;
		};

		pwm5: pwm5@300a015 {
			compatible = "allwinner,sunxi-pwm5";
			reg = <0x0 0x0300a015 0x0 0x4>;
			reg_base = <0x0300a000>;
		};

		ac200: ac200{
			compatible = "allwinner,sunxi-ac200";
			status = "okay";
		};

		pio: pinctrl@300b000 {
			compatible = "allwinner,sun50iw9-pinctrl";
			reg = <0x0 0x0300b000 0x0 0x400>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;
			vcc-pf-supply = <&reg_pio1_8>;
			vcc-pfo-supply = <&reg_pio3_3>;

			uart0_ph_pins: uart0-ph-pins {
				pins = "PH0", "PH1";
				function = "uart0";
			};

			uart0_ph_sleep: uart0-ph-sleep {
				pins = "PH0", "PH1";
				function = "gpio_in";
			};

			sdc0_pins_a: sdc0@0 {
                                pins = "PF0", "PF1", "PF2",
                                       "PF3", "PF4", "PF5";
                                function = "sdc0";
                                drive-strength = <30>;
                                bias-pull-up;
                                power-source = <3300>;
                        };

                        sdc0_pins_b: sdc0@1 {
                                pins = "PF0", "PF1", "PF2",
                                       "PF3", "PF4", "PF5";
                                function = "sdc0";
                                drive-strength = <30>;
                                bias-pull-up;
                                power-source = <1800>;
                        };

                        sdc0_pins_c: sdc0@2 {
                                pins = "PF0", "PF1", "PF2",
                                       "PF3", "PF4", "PF5";
                                function = "gpio_in";
                        };

                        /* TODO: add jtag pin */
                        sdc0_pins_d: sdc0@3 {
                                pins = "PF2", "PF4";
                                function = "uart0";
                                drive-strength = <10>;
                                bias-pull-up;
                        };

                        sdc0_pins_e: sdc0@4 {
                                pins = "PF0", "PF1", "PF3",
                                        "PF5";
                                function = "jtag";
                                drive-strength = <10>;
                                bias-pull-up;
                        };

			sdc1_pins_a: sdc1@0 {
				pins = "PG0", "PG1", "PG2",
						 "PG3", "PG4", "PG5";
				function = "sdc1";
				drive-strength = <40>;
				bias-pull-up;
			};

			sdc1_pins_b: sdc1@1 {
				pins = "PG0", "PG1", "PG2",
						 "PG3", "PG4", "PG5";
				function = "gpio_in";
				bias-pull-up;
			};

			sdc2_pins_a: sdc2@0 {
				pins = "PC1", "PC5", "PC6",
						 "PC8", "PC9", "PC10", "PC11",
						 "PC13", "PC14", "PC15", "PC16";
				function = "sdc2";
				drive-strength = <30>;
				bias-pull-up;
			};

			sdc2_pins_b: sdc2@1 {
				pins = "PC0", "PC1", "PC5", "PC6",
						 "PC8", "PC9", "PC10", "PC11",
						 "PC13", "PC14", "PC15", "PC16";
				function = "gpio_in";
				bias-pull-up;
			};

			sdc2_pins_c: sdc2@2 {
				allwinner,pins = "PC0";
				allwinner,function = "sdc2";
				drive-strength = <30>;
				bias-pull-down;
			};

			nand0_pins_a: nand0@0 {
				pins = "PC0", "PC1", "PC2", "PC5",
						 "PC8", "PC9", "PC10", "PC11",
						 "PC12", "PC13", "PC14", "PC15",
						 "PC16";
				function = "nand0";
				drive-strength = <40>;
			};

			nand0_pins_b: nand0@1 {
				pins = "PC4", "PC6", "PC3", "PC7";
				function = "nand0";
				drive-strength = <40>;
				bias-pull-up;/* only RB&CE should be pulled up */
			};

			nand0_pins_c: nand0@2 {
				pins = "PC0", "PC1", "PC2", "PC3",
						 "PC4", "PC5", "PC6", "PC7",
						 "PC8", "PC9", "PC10", "PC11",
						 "PC12", "PC13", "PC14", "PC15",
						 "PC16";
				function = "gpio_in";
			};

			csi_mclk0_pins_a: csi_mclk0@0 {
				pins = "PG19";
				function = "csi_mclk0";
				drive-strength = <20>;
			};

			csi_mclk0_pins_b: csi_mclk0@1 {
				pins = "PG19";
				function = "gpio_in";
			};

			csi_mclk1_pins_a: csi_mclk1@0 {
				pins = "PE1";
				function = "csi_mclk1";
				drive-strength = <20>;
			};

			csi_mclk1_pins_b: csi_mclk1@1 {
				pins = "PE1";
				function = "gpio_in";
			};

			csi_cci0_pins_a: csi_cci0@0 {
				pins = "PG17","PG18";
				function = "csi_cci0";
				drive-strength = <20>;
			};

			csi_cci0_pins_b: csi_cci0@1 {
				pins = "PG17","PG18";
				function = "gpio_in";
			};

			csi_cci1_pins_a: csi_cci1@0 {
				pins = "PE20","PE21";
				function = "csi_cci1";
				drive-strength = <20>;
			};

			csi_cci1_pins_b: csi_cci1@1 {
				pins = "PE20","PE21";
				function = "gpio_in";
			};

			csi1_pins_a: csi1@0 {
				pins = "PE0", "PE2", "PE3", "PE4", "PE5",
						 "PE6", "PE7", "PE8", "PE9", "PE10", "PE11",
						 "PE12", "PE13", "PE14", "PE15", "PE16", "PE17",
						  "PE18", "PE19";
				function = "csi1";
				drive-strength = <10>;
			};

			csi1_pins_b: csi1@1 {
				pins = "PE0", "PE2", "PE3", "PE4", "PE5",
						 "PE6", "PE7", "PE8", "PE9", "PE10", "PE11",
						 "PE12", "PE13", "PE14", "PE15", "PE16", "PE17",
						  "PE18", "PE19";
				function = "gpio_in";
			};

		};

		r_pio: pinctrl@7022000 {
			compatible = "allwinner,sun50iw9-r-pinctrl";
			reg = <0x0 0x07022000 0x0 0x400>;
			clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
		};

		mmu_aw: iommu@30f0000 {
			compatible = "allwinner,iommu-v12-sun50iw9";
			reg = <0x0 0x030f0000 0x0 0x1000>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "iommu-irq";
			clocks = <&ccu CLK_BUS_IOMMU>;
			clock-names = "iommu";
			#iommu-cells = <2>;
		};

		sdc2: sdmmc@4022000 {
			compatible = "allwinner,sunxi-mmc-v4p6x";
			device_type = "sdc2";
			reg = <0x0 0x04022000 0x0 0x1000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH1_2X>,
				 <&ccu CLK_MMC2>,
				 <&ccu CLK_BUS_MMC2>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC2>;
			reset-names = "rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc2_pins_a &sdc2_pins_c>;
			pinctrl-1 = <&sdc2_pins_b>;
			bus-width = <8>;
			req-page-count = <2>;
			cap-mmc-highspeed;
			mmc-cache-ctrl;
			non-removable;
			/*max-frequency = <200000000>;*/
			max-frequency = <50000000>;
			cap-erase;
			mmc-high-capacity-erase-size;
			/*-- speed mode --*/
			/*sm0: DS26_SDR12*/
			/*sm1: HSSDR52_SDR25*/
			/*sm2: HSDDR52_DDR50*/
			/*sm3: HS200_SDR104*/
			/*sm4: HS400*/
			/*-- frequency point --*/
			/*f0: CLK_400K*/
			/*f1: CLK_25M*/
			/*f2: CLK_50M*/
			/*f3: CLK_100M*/
			/*f4: CLK_150M*/
			/*f5: CLK_200M*/
			sdc_tm4_sm0_freq0 = <0>;
			sdc_tm4_sm0_freq1 = <0>;
			sdc_tm4_sm1_freq0 = <0x00000000>;
			sdc_tm4_sm1_freq1 = <0>;
			sdc_tm4_sm2_freq0 = <0x00000000>;
			sdc_tm4_sm2_freq1 = <0>;
			sdc_tm4_sm3_freq0 = <0x05000000>;
			sdc_tm4_sm3_freq1 = <0x00000005>;
			sdc_tm4_sm4_freq0 = <0x00050000>;
			sdc_tm4_sm4_freq1 = <0x00000004>;
			sdc_tm4_sm4_freq0_cmd = <0>;
			sdc_tm4_sm4_freq1_cmd = <0>;
			/*vmmc-supply = <&reg_3p3v>;*/
			/*vqmc-supply = <&reg_3p3v>;*/
			/*vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			sunxi-power-save-mode;
			sunxi-dis-signal-vol-sw;
			ctl-spec-caps = <0x308>;
			status = "disabled";

		};

		sdc0: sdmmc@4020000 {
			compatible = "allwinner,sunxi-mmc-v4p1x";
			device_type = "sdc0";
			reg = <0x0 0x04020000 0x0 0x1000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH1_2X>,
				 <&ccu CLK_MMC0>,
				 <&ccu CLK_BUS_MMC0>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "rst";
			pinctrl-names = "default","mmc_1v8","sleep","uart_jtag";
			pinctrl-0 = <&sdc0_pins_a>;
                        pinctrl-1 = <&sdc0_pins_b>;
                        pinctrl-2 = <&sdc0_pins_c>;
                        pinctrl-3 = <&sdc0_pins_d &sdc0_pins_e>;
			max-frequency = <50000000>;
			bus-width = <4>;
			req-page-count = <2>;
			/*non-removable;*/
			/*broken-cd;*/
			/*cd-inverted*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			cap-sd-highspeed;
			cap-wait-while-busy;
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr4  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr8  = <1 0 0 0>;*/
			/*sunxi-dly-104M  = <1 0 0 0>;*/
			/*sunxi-dly-208M  = <1 0 0 0>;*/
			/*sunxi-dly-104M-ddr  = <1 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0>;*/
			ctl-spec-caps = <0x8>;
			status = "okay";
		};

		sdc1: sdmmc@4021000 {
			compatible = "allwinner,sunxi-mmc-v4p1x";
			device_type = "sdc1";
			reg = <0x0 0x04021000 0x0 0x1000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dcxo24M>,
				 <&ccu CLK_PLL_PERIPH1_2X>,
				 <&ccu CLK_MMC1>,
				 <&ccu CLK_BUS_MMC1>;
			clock-names = "osc24m","pll_periph","mmc","ahb";
			resets = <&ccu RST_BUS_MMC1>;
			reset-names = "rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc1_pins_a>;
			pinctrl-1 = <&sdc1_pins_b>;
			max-frequency = <50000000>;
			bus-width = <4>;
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			cap-sd-highspeed;
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*sd-uhs-sdr104;*/
			/*cap-sdio-irq;*/
			keep-power-in-suspend;
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0 0>;*/
			sunxi-dly-52M-ddr4  = <1 0 0 0 2>;
			/*sunxi-dly-52M-ddr8  = <1 0 0 0 0>;*/
			sunxi-dly-104M  = <1 0 0 0 1>;
			/*sunxi-dly-208M  = <1 1 0 0 0>;*/
			sunxi-dly-208M  = <1 0 0 0 1>;
			/*sunxi-dly-104M-ddr  = <1 0 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0 0>;*/
			ctl-spec-caps = <0x8>;
			status = "disabled";
		};

		nand0:nand0@4011000 {
			compatible = "allwinner,sun50iw9-nand";
			device_type = "nand0";
			reg = <0x0 0x04011000 0x0 0x1000>;/* nand0 */
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_PLL_PERIPH1_2X>,
				<&ccu CLK_NAND0>,
				 <&ccu CLK_NAND1>,
				 <&ccu CLK_BUS_NAND>,
				 <&ccu CLK_MBUS_NAND>;
			clock-names = "pll_periph","mclk","ecc", "bus", "mbus";
			resets = <&ccu RST_BUS_NAND>;
			reset-names = "rst";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
			pinctrl-1 = <&nand0_pins_c>;
			nand0_cache_level = <0x55aaaa55>;
			nand0_flush_cache_num = <0x55aaaa55>;
			nand0_capacity_level = <0x55aaaa55>;
			nand0_id_number_ctl = <0x55aaaa55>;
			nand0_print_level = <0x55aaaa55>;
			nand0_p0 = <0x55aaaa55>;
			nand0_p1 = <0x55aaaa55>;
			nand0_p2 = <0x55aaaa55>;
			nand0_p3 = <0x55aaaa55>;
			chip_code = "sun50iw9";
			status = "disabled";
			/*boot_crc="disabled";*/
		};


		mbus0: mbus-controller@47fa000 {
			compatible = "allwinner,sun50i-mbus";
			reg = <0x0 0x047fa000 0x0 0x1000>;
			#mbus-cells = <1>;
		};

		uart0: uart@5000000 {
			compatible = "allwinner,sun50i-uart";
			reg = <0x0 0x05000000 0x0 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_UART0>;
			resets = <&ccu RST_BUS_UART0>;
			uart0_port = <0>;
			uart0_type = <2>;
			status = "disabled";
		};

		uart1: uart@5000400 {
			compatible = "allwinner,sun50i-uart";
			reg = <0x0 0x05000400 0x0 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_UART1>;
			resets = <&ccu RST_BUS_UART1>;
			uart1_port = <1>;
			uart1_type = <4>;
			sunxi,uart-fifosize = <256>;
			status = "disabled";
		};

		uart2: uart@5000800 {
			compatible = "allwinner,sun50i-uart";
			reg = <0x0 0x05000800 0x0 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_UART2>;
			resets = <&ccu RST_BUS_UART2>;
			uart2_port = <2>;
			uart2_type = <4>;
			sunxi,uart-fifosize = <256>;
			status = "disabled";
		};

		uart3: uart@5000c00 {
			compatible = "allwinner,sun50i-uart";
			reg = <0x0 0x05000c00 0x0 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_UART3>;
			resets = <&ccu RST_BUS_UART3>;
			uart3_port = <3>;
			uart3_type = <4>;
			sunxi,uart-fifosize = <256>;
			status = "disabled";
		};

		uart4: uart@5001000 {
			compatible = "allwinner,sun50i-uart";
			reg = <0x0 0x05001000 0x0 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_UART4>;
			resets = <&ccu RST_BUS_UART4>;
			uart4_port = <4>;
			uart4_type = <4>;
			sunxi,uart-fifosize = <256>;
			status = "disabled";
		};

		uart5: uart@5001400 {
			compatible = "allwinner,sun50i-uart";
			reg = <0x0 0x05001400 0x0 0x400>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_UART5>;
			resets = <&ccu RST_BUS_UART5>;
			uart5_port = <5>;
			uart5_type = <2>;
			sunxi,uart-fifosize = <256>;
			status = "disabled";
		};

		twi0: twi@5002000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi0";
			reg = <0x0 0x05002000 0x0 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C0>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_I2C0>;
			dmas = <&dma 43>, <&dma 43>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		twi1: twi@5002400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi1";
			reg = <0x0 0x05002400 0x0 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C1>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_I2C1>;
			dmas = <&dma 44>, <&dma 44>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		twi2: twi@5002800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi2";
			reg = <0x0 0x05002800 0x0 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C2>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_I2C2>;
			dmas = <&dma 45>, <&dma 45>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		twi3: twi@5002c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi3";
			reg = <0x0 0x05002c00 0x0 0x400>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C3>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_I2C3>;
			dmas = <&dma 46>, <&dma 46>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		twi4: twi@5003000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi4";
			reg = <0x0 0x05003000 0x0 0x400>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C4>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_I2C4>;
			dmas = <&dma 47>, <&dma 47>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		twi5: twi@7081400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi5";
			reg = <0x0 0x07081400 0x0 0x400>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_APB2_I2C>;
			clock-names = "bus";
			resets = <&r_ccu RST_R_APB2_I2C>;
			dmas = <&dma 48>, <&dma 48>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		spi0: spi@5010000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-spi";
			device_type = "spi0";
			reg = <0x0 0x05010000 0x0 0x1000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>;
			clock-names = "pll", "mod", "bus";
			resets = <&ccu RST_BUS_SPI0>;
			clock-frequency = <100000000>;
			spi0_cs_number = <1>;
			spi0_cs_bitmap = <1>;
			dmas = <&dma 22>, <&dma 22>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		spi1: spi@5011000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-spi";
			device_type = "spi1";
			reg = <0x0 0x05011000 0x0 0x1000>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI1>, <&ccu CLK_BUS_SPI1>;
			clock-names = "pll", "mod", "bus";
			resets = <&ccu RST_BUS_SPI1>;
			clock-frequency = <100000000>;
			spi1_cs_number = <1>;
			spi1_cs_bitmap = <1>;
			dmas = <&dma 23>, <&dma 23>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		ths: thermal-sensor@5070400 {
			compatible = "allwinner,sun50iw9p1-ths";
			reg = <0x0 0x05070400 0x0 0x400>;
			clocks = <&ccu CLK_BUS_THS>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_THS>;
			nvmem-cells = <&ths_calib>;
			nvmem-cell-names = "calibration";
			#thermal-sensor-cells = <1>;
		};

		gpadc: gpadc@5070000 {
			compatible = "allwinner,sunxi-gpadc";
			reg = <0x0 0x05070000 0x0 0x3ff>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_GPADC>;
			clock-names = "bus";
			resets = <&ccu RST_BUS_GPADC>;
			status = "disabled";
		};

		keyboard: keyboard@5070800 {
			compatible = "allwinner,keyboard_1350mv";
			reg = <0x0 0x05070800 0x0 0x400>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>;
			clocks = <&ccu CLK_BUS_LRADC>;
			resets = <&ccu RST_BUS_LRADC>;
			status = "disabled";
		};

		/* audio driver use harmony ADM */
		/* audio dirver module -> audio codec */
		codec:codec@5096000 {
			compatible	= "allwinner,sunxi-snd-codec";
			reg		= <0x0 0x05096000 0x0 0x31C>;
			/* clocks	= <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_codec_1x>; */
			resets		= <&ccu RST_BUS_AUDIO_CODEC>;
			clocks		= <&ccu CLK_PLL_AUDIO>,
					  <&ccu CLK_PLL_AUDIO_4X>,
					  <&ccu CLK_AUDIO>,
					  <&ccu CLK_BUS_AUDIO_CODEC>;
			clock-names	= "clk_pll_audio",
					  "clk_pll_audio_4x",
					  "clk_audio",
					  "clk_bus_audio";
			dmas		= <&dma 6>, <&dma 6>;
			dma-names	= "tx", "rx";
			status		= "disabled";
		};

		/* audio dirver module -> audio hub */
		ahub:ahub@5097000 {
			compatible	= "allwinner,sunxi-snd-ahub";
			reg		= <0x0 0x05097000 0x0 0xAEC>;
			/* clocks	= <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_ahub>; */
			resets		= <&ccu RST_BUS_AUDIO_HUB>;
			clocks		= <&ccu CLK_PLL_AUDIO>,
					  <&ccu CLK_PLL_AUDIO_4X>,
					  <&ccu CLK_AUDIO_HUB>,
					  <&ccu CLK_BUS_AUDIO_HUB>;
			clock-names	= "clk_pll_audio",
					  "clk_pll_audio_4x",
					  "clk_audio_hub",
					  "clk_bus_audio_hub";
			dmas		= <&dma 3>, <&dma 3>;
			dma-names	= "tx", "rx";
			status		= "disabled";
		};

/*------------------------------------------------------------------------------
		codec:codec@5096000 {
			#sound-dai-cells = <0>;
			compatible	= "allwinner,sunxi-snd-codec";
			reg		= <0x0 0x05096000 0x0 0x31C>;
			resets		= <&ccu RST_BUS_AUDIO_CODEC>;
			clocks		= <&ccu CLK_PLL_AUDIO_4X>,
					  <&ccu CLK_AUDIO>,
					  <&ccu CLK_BUS_AUDIO_CODEC>;
			clock-names	= "clk_pll_audio_4x",
					  "clk_audio",
					  "clk_bus_audio";
			status = "disabled";
		};

		codec_plat:codec_plat {
			#sound-dai-cells = <0>;
			compatible	= "allwinner,sunxi-snd-plat-aaudio";
			playback_cma	= <128>;
			capture_cma	= <128>;
			tx_fifo_size	= <128>;
			rx_fifo_size	= <128>;
			dac_txdata	= <0x05096020>;
			adc_txdata	= <0x05096040>;
			dmas		= <&dma 6>, <&dma 6>;
			dma-names	= "tx", "rx";
			status = "disabled";
		};

		codec_mach:codec_mach {
			compatible = "allwinner,sunxi-snd-mach";
			soundcard-mach,name = "audiocodec";
			soundcard-mach,playback-only;
			soundcard-mach,pin-switches = "LINEOUT";
			soundcard-mach,routing = "LINEOUT", "LINEOUTL",
						 "LINEOUT", "LINEOUTR";
			status = "disabled";
			soundcard-mach,cpu {
				sound-dai = <&codec_plat>;
			};
			soundcard-mach,codec {
				sound-dai = <&codec>;
				soundcard-mach,pll-fs	= <4>;
			};
		};

		spdif_plat:spdif_plat@5093000 {
			#sound-dai-cells = <0>;
			compatible	= "allwinner,sunxi-snd-plat-spdif";
			reg		= <0x0 0x05093000 0x0 0x40>;
			resets		= <&ccu RST_BUS_SPDIF>;
			clocks		= <&ccu CLK_PLL_AUDIO_4X>,
					  <&ccu CLK_SPDIF>,
					  <&ccu CLK_BUS_SPDIF>;
			clock-names	= "clk_pll_audio_4x",
					  "clk_spdif",
					  "clk_bus_spdif";
			pll-fs		= <4>;
			dmas		= <&dma 2>, <&dma 2>;
			dma-names	= "tx", "rx";
			playback_cma	= <128>;
			capture_cma	= <128>;
			tx_fifo_size	= <128>;
			rx_fifo_size	= <64>;
			status = "disabled";
		};

		spdif_mach:spdif_mach {
			compatible = "allwinner,sunxi-snd-mach";
			soundcard-mach,name = "sndspdif";
			status = "disabled";
			soundcard-mach,cpu {
				sound-dai = <&spdif_plat>;
				soundcard-mach,pll-fs	= <4>;
			};
			soundcard-mach,codec {
			};
		};

		ahub_dam_plat:ahub_dam_plat@5097000 {
			#sound-dai-cells = <0>;
			compatible	= "allwinner,sunxi-snd-plat-ahub_dam";
			reg		= <0x0 0x05097000 0x0 0xAEC>;
			resets		= <&ccu RST_BUS_AUDIO_HUB>;
			clocks		= <&ccu CLK_PLL_AUDIO>,
					  <&ccu CLK_PLL_AUDIO_4X>,
					  <&ccu CLK_AUDIO_HUB>,
					  <&ccu CLK_BUS_AUDIO_HUB>;
			clock-names	= "clk_pll_audio",
					  "clk_pll_audio_4x",
					  "clk_audio_hub",
					  "clk_bus_audio_hub";
			status		= "disabled";
		};

		ahub_dam_mach:ahub_dam_mach {
			compatible = "allwinner,sunxi-snd-mach";
			soundcard-mach,name = "ahubdam";
			status		= "disabled";
			soundcard-mach,cpu {
				sound-dai = <&ahub_dam_plat>;
			};
			soundcard-mach,codec {
			};
		};

		ahub0_plat:ahub0_plat {
			#sound-dai-cells = <0>;
			compatible	= "allwinner,sunxi-snd-plat-ahub";
			apb_num		= <0>;
			dmas		= <&dma 3>, <&dma 3>;
			dma-names	= "tx", "rx";
			playback_cma	= <128>;
			capture_cma	= <128>;
			tx_fifo_size	= <128>;
			rx_fifo_size	= <128>;
			status		= "disabled";
		};

		ahub1_plat:ahub1_plat {
			#sound-dai-cells = <0>;
			compatible	= "allwinner,sunxi-snd-plat-ahub";
			apb_num		= <1>;
			dmas		= <&dma 4>, <&dma 4>;
			dma-names	= "tx", "rx";
			playback_cma	= <128>;
			capture_cma	= <128>;
			tx_fifo_size	= <128>;
			rx_fifo_size	= <128>;
			status		= "disabled";
		};

		ahub2_plat:ahub2_plat {
			#sound-dai-cells = <0>;
			compatible	= "allwinner,sunxi-snd-plat-ahub";
			apb_num		= <2>;
			dmas		= <&dma 5>, <&dma 5>;
			dma-names	= "tx", "rx";
			playback_cma	= <128>;
			capture_cma	= <128>;
			tx_fifo_size	= <128>;
			rx_fifo_size	= <128>;
			status		= "disabled";
		};

		ahub3_plat:ahub3_plat {
			#sound-dai-cells = <0>;
			compatible	= "allwinner,sunxi-snd-plat-ahub";
			apb_num		= <2>;
			dmas		= <&dma 5>, <&dma 5>;
			dma-names	= "tx", "rx";
			playback_cma	= <128>;
			capture_cma	= <128>;
			tx_fifo_size	= <128>;
			rx_fifo_size	= <128>;
			status		= "disabled";
		};

		ahub0_mach:ahub0_mach {
			compatible = "allwinner,sunxi-snd-mach";
			soundcard-mach,name = "ahubi2s0";
			status		= "disabled";
			soundcard-mach,cpu {
				sound-dai = <&ahub0_plat>;
			};
			soundcard-mach,codec {
			};
		};

		ahub1_mach:ahub1_mach {
			compatible = "allwinner,sunxi-snd-mach";
			soundcard-mach,name = "ahubhdmi";
			status		= "disabled";
			soundcard-mach,cpu {
				sound-dai = <&ahub1_plat>;
			};
			soundcard-mach,codec {
			};
		};

		ahub2_mach:ahub2_mach {
			compatible = "allwinner,sunxi-snd-mach";
			soundcard-mach,name = "ahubi2s2";
			status		= "disabled";
			soundcard-mach,cpu {
				sound-dai = <&ahub2_plat>;
			};
			soundcard-mach,codec {
			};
		};

		ahub3_mach:ahub3_mach {
			compatible = "allwinner,sunxi-snd-mach";
			soundcard-mach,name = "ahubi2s3";
			status		= "disabled";
			soundcard-mach,cpu {
				sound-dai = <&ahub3_plat>;
			};
			soundcard-mach,codec {
			};
		};
------------------------------------------------------------------------------*/

		gpio_para:gpio_para {
			device_type = "gpio_para";
			compatible = "allwinner,sunxi-init-gpio";
			status = "disabled";
		};

		mdio0: mdio0@5020048 {
			compatible = "allwinner,sunxi-mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x05020048 0x0 0x8>;
			status = "okay";
			gmac0_phy0: ethernet-phy@1 {
				/* RTL8211F (0x001cc916) */
				reg = <1>;
				max-speed = <1000>;  /* Max speed capability */
				reset-gpios = <&pio PI 6 GPIO_ACTIVE_LOW>;
				/* PHY datasheet rst time */
				reset-assert-us = <10000>;
				reset-deassert-us = <150000>;
			};
		};

		gmac0: gmac0@5020000 {
			compatible = "allwinner,sunxi-gmac";
			reg = <0x0 0x05020000 0x0 0x10000>,
			      <0x0 0x03000030 0x0 0x4>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gmacirq";
			clocks = <&ccu CLK_BUS_EMAC0>, <&ccu CLK_EMAC_25M>;
			clock-names = "gmac", "phy25m";
			resets = <&ccu RST_BUS_EMAC0>;
			phy-handle = <&gmac0_phy0>;
			status = "disabled";
		};

		usbc0: usbc0@0 {
			device_type = "usbc0";
			compatible = "allwinner,sunxi-otg-manager";
			usb_port_type = <2>;
			usb_detect_type = <1>;
			usb_detect_mode = <0>;
			usb_id_gpio;
			usb_det_vbus_gpio;
			usb_drv_vbus_gpio;
			usb_host_init_state = <0>;
			usb_regulator_io = "nocare";
			usb_wakeup_suspend = <0>;
			usb_luns = <3>;
			usb_serial_unique = <0>;
			usb_serial_number = "20080411";
			rndis_wceis = <1>;
			wakeup-source;
		};

		udc: udc-controller@5100000 {
			compatible = "allwinner,sunxi-udc";
			reg = <0x0 0x05100000 0x0 0x1000>,
			      <0x0 0x00000000 0x0 0x100>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			clocks = <&ccu CLK_BUS_OTG>, <&ccu CLK_USB_PHY0>;
			clock-names = "bus_otg", "phy";
			resets = <&ccu RST_BUS_OTG>, <&ccu RST_USB_PHY0>;
			reset-names = "otg", "phy";
		};

		ehci0: ehci0-controller@5101000 {
			compatible = "allwinner,sunxi-ehci0";
			reg = <0x0 0x05101000 0x0 0xFFF>,
			      <0x0 0x00000000 0x0 0x100>,
			      <0x0 0x05100000 0x0 0x1000>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_USB_PHY0>;
			clock-names = "bus_hci", "phy";
			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_USB_PHY0>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <0>;
		};

		ohci0: ohci0-controller@5101400 {
			compatible = "allwinner,sunxi-ohci0";
			reg = <0x0 0x05101400 0x0 0xFFF>,
			      <0x0 0x00000000 0x0 0x100>,
			      <0x0 0x05100000 0x0 0x1000>;
			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>, <&ccu CLK_USB_PHY0>;
			clock-names = "bus_hci", "ohci", "phy";
			resets = <&ccu RST_BUS_OHCI0>, <&ccu RST_USB_PHY0>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <0>;
		};

		usbc1: usbc1@0 {
			device_type = "usbc1";
			usb_drv_vbus_gpio;
			usb_host_init_state = <1>;
			usb_regulatior_io = "nocare";
			usb_wakeup_suspend = <0>;
			wakeup-source;
		};

		ehci1: ehci1-controller@5200000 {
			compatible = "allwinner,sunxi-ehci1";
			reg = <0x0 0x05200000 0x0 0xFFF>,
			      <0x0 0x00000000 0x0 0x100>,
			      <0x0 0x05100000 0x0 0x1000>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_USB_PHY1>;
			clock-names = "bus_hci", "phy";
			resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_USB_PHY1>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <1>;
		};

		ohci1: ohci1-controller@5200400 {
			compatible = "allwinner,sunxi-ohci1";
			reg = <0x0 0x05200400 0x0 0xFFF>,
			      <0x0 0x00000000 0x0 0x100>,
			      <0x0 0x05100000 0x0 0x1000>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI1>, <&ccu CLK_USB_OHCI1>, <&ccu CLK_USB_PHY1>;
			clock-names = "bus_hci", "ohci", "phy";
			resets = <&ccu RST_BUS_OHCI1>, <&ccu RST_USB_PHY1>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <1>;
		};

		usbc2: usbc2@0 {
			device_type = "usbc2";
			usb_drv_vbus_gpio;
			usb_host_init_state = <1>;
			usb_regulatior_io = "nocare";
			usb_wakeup_suspend = <0>;
			wakeup-source;
		};

		ehci2: ehci2-controller@5310000 {
			compatible = "allwinner,sunxi-ehci2";
			reg = <0x0 0x05310000 0x0 0xFFF>,
			      <0x0 0x00000000 0x0 0x100>,
			      <0x0 0x05100000 0x0 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_USB_PHY2>;
			clock-names = "bus_hci", "phy";
			resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_USB_PHY2>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <2>;
		};

		ohci2: ohci2-controller@5310400 {
			compatible = "allwinner,sunxi-ohci2";
			reg = <0x0 0x05310400 0x0 0xFFF>,
			      <0x0 0x00000000 0x0 0x100>,
			      <0x0 0x05100000 0x0 0x1000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI2>, <&ccu CLK_USB_OHCI2>, <&ccu CLK_USB_PHY2>;
			clock-names = "bus_hci", "ohci", "phy";
			resets = <&ccu RST_BUS_OHCI2>, <&ccu RST_USB_PHY2>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <2>;
		};

		usbc3: usbc3@0 {
			device_type = "usbc3";
			usb_drv_vbus_gpio;
			usb_host_init_state = <1>;
			usb_regulatior_io = "nocare";
			usb_wakeup_suspend = <0>;
			wakeup-source;
		};

		ehci3: ehci3-controller@5311000 {
			compatible = "allwinner,sunxi-ehci3";
			reg = <0x0 0x05311000 0x0 0xFFF>,
			      <0x0 0x00000000 0x0 0x100>,
			      <0x0 0x05100000 0x0 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_USB_PHY3>;
			clock-names = "bus_hci", "phy";
			resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_USB_PHY3>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <3>;
		};

		ohci3: ohci3-controller@5311400 {
			compatible = "allwinner,sunxi-ohci3";
			reg = <0x0 0x05311400 0x0 0xFFF>,
			      <0x0 0x00000000 0x0 0x100>,
			      <0x0 0x05100000 0x0 0x1000>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI3>, <&ccu CLK_USB_OHCI3>, <&ccu CLK_USB_PHY3>;
			clock-names = "bus_hci", "ohci", "phy";
			resets = <&ccu RST_BUS_OHCI3>, <&ccu RST_USB_PHY3>;
			reset-names = "hci", "phy";
			hci_ctrl_no = <3>;
		};

		hdmi: hdmi@6000000 {
			compatible = "allwinner,sunxi-hdmi";
			reg = <0x0 0x06000000 0x0 0x100000>;
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_HDMI>,
				<&ccu CLK_HDMI>,
				<&ccu CLK_HDMI_SLOW>,
				<&ccu CLK_HDMI_CEC>,
				<&ccu CLK_BUS_HDMI_HDCP>,
				<&ccu CLK_HDMI_HDCP>,
				<&ccu CLK_TCON_TV0>;
			clock-names = "clk_bus_hdmi",
				      "clk_hdmi",
				      "clk_ddc",
				      "clk_cec",
				      "clk_bus_hdcp",
				      "clk_hdcp",
				      "clk_tcon_tv";
			resets = <&ccu RST_BUS_HDMI_SUB>,
				<&ccu RST_BUS_HDMI_MAIN>,
				<&ccu RST_BUS_HDMI_HDCP>;
			reset-names = "rst_bus_sub",
				      "rst_bus_main",
				      "rst_bus_hdcp";
			assigned-clocks = <&ccu CLK_HDMI>,
				<&ccu CLK_HDMI_HDCP>;
			assigned-clock-parents = <&ccu CLK_PLL_VIDEO2>,
				<&ccu CLK_PLL_PERIPH1>;
			assigned-clock-rates = <0>, <0>;

			status = "okay";
		};

		nmi_intc: interrupt-controller@7010320 {
			compatible = "allwinner,sun8i-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x0 0x07010320 0 0xc>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			pad-control-v1 = <0x07000208>;
		};

		s_cir0: s_cir@7040000 {
			compatible = "allwinner,s_cir";
			reg = <0x0 0x07040000 0x0 0x400>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_R_APB1_BUS_IR>, <&dcxo24M>, <&r_ccu CLK_R_APB1_IR>;
			clock-names = "bus", "pclk", "mclk";
			resets = <&r_ccu RST_R_APB1_BUS_IR>;
			status = "disabled";
		};

		rfkill: rfkill {
			compatible = "allwinner,sunxi-rfkill";
			status = "disabled";
		};

		addr_mgt: addr_mgt {
			compatible = "allwinner,sunxi-addr_mgt";
			status = "disabled";
		};

		btlpm: btlpm {
			compatible = "allwinner,sunxi-btlpm";
			status = "disabled";
		};
	};

	uboot_disp: uboot_disp@1000000 {
		compatible = "allwinner,sunxi-disp";
		reg = <0x0 0x01000000 0x0 0x01400000>, /* de */
		      <0x0 0x06510000 0x0 0x200>, /* display_if_top */
		      <0x0 0x06511000 0x0 0x1000>, /* tcon_lcd0 */
		      <0x0 0x06512000 0x0 0x1000>, /* tcon_lcd1 */
		      <0x0 0x06515000 0x0 0x1000>, /* tcon_tv0 */
		      <0x0 0x06516000 0x0 0x1000>; /* tcon_tv1 */
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* DE */
			     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd0 */
			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd1 */
			     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, /* tcon_tv0 */
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* tcon_tv1 */
		clocks = <&clk_de>,
			 <&clk_display_top>,
			 <&clk_tcon_lcd>,
			 <&clk_tcon_lcd1>,
			 <&clk_tcon_tv>,
			 <&clk_tcon_tv1>,
			 <&clk_lvds>;
		boot_disp = <0>;
		fb_base = <0>;
	};

	uboot_hdmi: uboot_hdmi@6000000 {
		compatible = "allwinner,sunxi-hdmi";
		reg = <0x0 0x06000000 0x0 0x100000>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_hdmi>, <&clk_hdmi_slow>,
			 <&clk_hdmi_hdcp>, <&clk_hdmi_cec>;
	};

	thermal-zones{
		cpu_thermal_zone{
			polling-delay-passive = <500>;
			polling-delay = <1000>;
			thermal-sensors = <&ths 2>;
			sustainable-power = <927>;

			cpu_trips: trips{
				cpu_threshold: trip-point@0 {
					temperature = <70000>;
					type = "passive";
					hysteresis = <0>;
				};
				cpu_target: trip-point@1 {
					temperature = <90000>;
					type = "passive";
					hysteresis = <0>;
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_target>;
					cooling-device = <&cpu0
							  THERMAL_NO_LIMIT
							  THERMAL_NO_LIMIT>;
					contribution = <1024>;
				};
				map1{
					trip = <&cpu_target>;
					cooling-device = <&gpu
							  THERMAL_NO_LIMIT
							  THERMAL_NO_LIMIT>;
					contribution = <1024>;
				};
			};
		};

		ddr_thermal_zone {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&ths 3>;
		};

		gpu_thermal_zone {
			polling-delay-passive = <500>;
			polling-delay = <1000>;
			thermal-sensors = <&ths 0>;
			sustainable-power = <1100>;
		};

		ve_thermal_zone {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&ths 1>;
		};
	};
};