Lines Matching full:imm
28 LogicalImmediate LogicalImmediate::Create(uint64_t imm, int width) in Create() argument
30 if ((imm == 0ULL) || (imm == ~0ULL) || in Create()
31 … ((width != RegXSize) && (((imm >> width) != 0) || (imm == (~0ULL >> (RegXSize - width)))))) { in Create()
41 if ((imm & mask) != ((imm >> size) & mask)) { in Create()
51 imm &= mask; in Create()
53 if (IsShiftedMask_64(imm)) { in Create()
54 i = CountTrailingZeros64(imm); in Create()
56 cto = CountTrailingOnes64(imm >> i); in Create()
58 imm |= ~mask; in Create()
59 if (!IsShiftedMask_64(~imm)) { in Create()
63 uint32_t clo = CountLeadingOnes64(imm); in Create()
65 cto = clo + CountTrailingOnes64(imm) - (static_cast<uint32_t>(RegXSize) - size); in Create()
108 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldp() local
110 imm >>= 3; // 3: 64 RegSise, imm/8 to remove trailing zeros in Ldp()
112 imm >>= 2; // 2: 32 RegSise, imm/4 to remove trailing zeros in Ldp()
114 uint32_t instructionCode = Sf(sf) | op | LoadAndStorePairImm(imm) | Rt2(rt2.GetId()) | in Ldp()
142 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stp() local
144 imm >>= 3; // 3: 64 RegSise, imm/8 to remove trailing zeros in Stp()
146 imm >>= 2; // 2: 32 RegSise, imm/4 to remove trailing zeros in Stp()
148 uint32_t instructionCode = Sf(sf) | op | LoadAndStorePairImm(imm) | Rt2(rt2.GetId()) | in Stp()
175 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldp() local
179 imm >>= 2; in Ldp()
183 imm >>= 3; in Ldp()
187 imm >>= 4; in Ldp()
194 uint32_t instructionCode = opc | op | LoadAndStorePairImm(imm) | Rt2(vt2.GetId()) | in Ldp()
221 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stp() local
225 imm >>= 2; in Stp()
229 imm >>= 3; in Stp()
233 imm >>= 4; in Stp()
240 uint32_t instructionCode = opc | op | LoadAndStorePairImm(imm) | Rt2(vt2.GetId()) | in Stp()
281 uint64_t imm = GetImmOfLdr(operand, scale, regX); in Ldr() local
284 …uint32_t instructionCode = ((regX && (scale == Scale::Q)) << 30) | op | LoadAndStoreImm(imm, isSig… in Ldr()
324 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Str() local
330 imm >>= 3; // 3: 64 RegSise, imm/8 to remove trailing zeros in Str()
332 imm >>= 2; // 2: 32 RegSise, imm/4 to remove trailing zeros in Str()
347 uint32_t instructionCode = (regX << 30) | op | LoadAndStoreImm(imm, isSigned) | in Str()
361 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldur() local
363 uint32_t instructionCode = (regX << 30) | op | LoadAndStoreImm(imm, true) | in Ldur()
373 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stur() local
375 uint32_t instructionCode = (regX << 30) | op | LoadAndStoreImm(imm, true) | in Stur()
380 void AssemblerAarch64::Mov(const Register &rd, const Immediate &imm) in Mov() argument
384 uint64_t immValue = static_cast<uint64_t>(imm.Value()); in Mov()
490 static uint64_t UpdateImm(uint64_t imm, unsigned idx, bool clear) in UpdateImm() argument
494 imm &= ~(HWORD_MASK << idx); in UpdateImm()
497 imm |= HWORD_MASK << idx; in UpdateImm()
499 return imm; in UpdateImm()
502 bool AssemblerAarch64::TrySequenceOfOnes(const Register &rd, uint64_t imm) in TrySequenceOfOnes() argument
509 int64_t himm = (imm >> shift) & HWORD_MASK; in TrySequenceOfOnes()
537 uint64_t orrImm = imm; in TrySequenceOfOnes()
541 uint64_t himm = (imm >> shift) & HWORD_MASK; in TrySequenceOfOnes()
562 Movk(rd, (imm >> firstMovkShift) & HWORD_MASK, firstMovkShift); in TrySequenceOfOnes()
564 Movk(rd, (imm >> secondMovkShift) & HWORD_MASK, secondMovkShift); in TrySequenceOfOnes()
569 bool AssemblerAarch64::TryReplicateHWords(const Register &rd, uint64_t imm) in TryReplicateHWords() argument
574 uint64_t halfWord = (imm >> idx) & HWORD_MASK; in TryReplicateHWords()
595 imm16 = (imm >> shift) & HWORD_MASK; in TryReplicateHWords()
602 // 3 : 3 means repeat 3 times, Imm encode has been done. in TryReplicateHWords()
608 imm16 = (imm >> shift) & HWORD_MASK; in TryReplicateHWords()
619 void AssemblerAarch64::EmitMovInstruct(const Register &rd, uint64_t imm, in EmitMovInstruct() argument
625 imm = ~imm; in EmitMovInstruct()
629 if (imm != 0) { in EmitMovInstruct()
630 int lz = static_cast<int>(CountLeadingZeros64(imm)); in EmitMovInstruct()
631 int tz = static_cast<int>(CountTrailingZeros64(imm)); in EmitMovInstruct()
636 uint64_t imm16 = (imm >> firstshift) & HWORD_MASK; in EmitMovInstruct()
639 imm = ~imm; in EmitMovInstruct()
648 imm16 = (imm >> firstshift) & HWORD_MASK; in EmitMovInstruct()
657 void AssemblerAarch64::Movz(const Register &rd, uint64_t imm, int shift) in Movz() argument
659 MovWide(MoveOpCode::MOVZ, rd, imm, shift); in Movz()
662 void AssemblerAarch64::Movk(const Register &rd, uint64_t imm, int shift) in Movk() argument
664 MovWide(MoveOpCode::MOVK, rd, imm, shift); in Movk()
667 void AssemblerAarch64::Movn(const Register &rd, uint64_t imm, int shift) in Movn() argument
669 MovWide(MoveOpCode::MOVN, rd, imm, shift); in Movn()
672 void AssemblerAarch64::MovWide(uint32_t op, const Register &rd, uint64_t imm, int shift) in MovWide() argument
674 uint32_t imm_field = (imm << MOV_WIDE_Imm16_LOWBITS) & MOV_WIDE_Imm16_MASK; in MovWide()
681 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const LogicalImmediate &imm) in Orr() argument
683 BitWiseOpImm(ORR_Imm, rd, rn, imm.Value()); in Orr()
686 void AssemblerAarch64::And(const Register &rd, const Register &rn, const LogicalImmediate &imm) in And() argument
688 BitWiseOpImm(AND_Imm, rd, rn, imm.Value()); in And()
691 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const LogicalImmediate &imm) in Ands() argument
693 BitWiseOpImm(ANDS_Imm, rd, rn, imm.Value()); in Ands()
714 …emblerAarch64::BitWiseOpImm(BitwiseOpCode op, const Register &rd, const Register &rn, uint64_t imm) in BitWiseOpImm() argument
716 uint32_t code = Sf(!rd.IsW()) | op | imm | Rn(rn.GetId()) | Rd(rd.GetId()); in BitWiseOpImm()
771 int64_t imm = static_cast<int64_t>(operand.ImmediateValue()); in Add() local
772 if (imm < 0) { in Add()
773 AddSubImm(SUB_Imm, rd, rn, false, -1 * imm); in Add()
775 AddSubImm(ADD_Imm, rd, rn, false, imm); in Add()
802 int64_t imm = static_cast<int64_t>(operand.ImmediateValue()); in Sub() local
803 if (imm < 0) { in Sub()
804 AddSubImm(ADD_Imm, rd, rn, false, -1 * imm); in Sub()
806 AddSubImm(SUB_Imm, rd, rn, false, imm); in Sub()
830 bool AssemblerAarch64::IsAddSubImm(uint64_t imm) in IsAddSubImm() argument
833 if (imm <= IMM12_MASK) { in IsAddSubImm()
837 if (((imm & IMM12_MASK) == 0) && ((imm & ~IMM12_MASK) <= IMM12_MASK)) { in IsAddSubImm()
843 …64::AddSubImm(AddSubOpCode op, const Register &rd, const Register &rn, bool setFlags, uint64_t imm) in AddSubImm() argument
845 ASSERT(IsAddSubImm(imm)); in AddSubImm()
848 uint64_t imm12 = imm & (~IMM12_MASK); in AddSubImm()
852 imm12 = imm; in AddSubImm()
904 void AssemblerAarch64::B(int32_t imm) in B() argument
906 uint32_t code = BranchOpCode::Branch | ((imm << BRANCH_Imm26_LOWBITS) & BRANCH_Imm26_MASK); in B()
924 void AssemblerAarch64::Bl(int32_t imm) in Bl() argument
926 uint32_t code = CallOpCode::BL | ((imm << BRANCH_Imm26_LOWBITS) & BRANCH_Imm26_MASK); in Bl()
945 void AssemblerAarch64::B(Condition cond, int32_t imm) in B() argument
947 uint32_t code = BranchOpCode::BranchCond | BranchImm19(imm) | cond; in B()
967 void AssemblerAarch64::Cbz(const Register &rt, int32_t imm) in Cbz() argument
969 uint32_t code = Sf(!rt.IsW()) | BranchOpCode::CBZ | BranchImm19(imm) | rt.GetId(); in Cbz()
973 void AssemblerAarch64::Cbnz(const Register &rt, int32_t imm) in Cbnz() argument
975 uint32_t code = Sf(!rt.IsW()) | BranchOpCode::CBNZ | BranchImm19(imm) | rt.GetId(); in Cbnz()
987 void AssemblerAarch64::Tbz(const Register &rt, int32_t bitPos, int32_t imm) in Tbz() argument
991 uint32_t imm14 = (imm << BRANCH_Imm14_LOWBITS) & BRANCH_Imm14_MASK; in Tbz()
1004 void AssemblerAarch64::Tbnz(const Register &rt, int32_t bitPos, int32_t imm) in Tbnz() argument
1008 uint32_t imm14 = (imm <<BRANCH_Imm14_LOWBITS) & BRANCH_Imm14_MASK; in Tbnz()
1013 void AssemblerAarch64::Tst(const Register &rn, const LogicalImmediate &imm) in Tst() argument
1015 Ands(Register(Zero, rn.GetType()), rn, imm); in Tst()
1127 void AssemblerAarch64::Brk(const Immediate &imm) in Brk() argument
1130 (static_cast<uint32_t>(imm.Value()) << BRK_Imm16_LOWBITS) & BRK_Imm16_MASK; in Brk()
1138 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in GetImmOfLdr() local
1141 imm >>= 1; in GetImmOfLdr()
1144 imm >>= 3; // 3: 64 RegSise, imm/8 to remove trailing zeros in GetImmOfLdr()
1146 imm >>= 2; // 2: 32 RegSise, imm/4 to remove trailing zeros in GetImmOfLdr()
1150 return imm; in GetImmOfLdr()