Lines Matching refs:pctl
65 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) in sunxi_pinctrl_find_group_by_name() argument
69 for (i = 0; i < pctl->ngroups; i++) { in sunxi_pinctrl_find_group_by_name()
70 struct sunxi_pinctrl_group *grp = pctl->groups + i; in sunxi_pinctrl_find_group_by_name()
80 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, in sunxi_pinctrl_find_function_by_name() argument
83 struct sunxi_pinctrl_function *func = pctl->functions; in sunxi_pinctrl_find_function_by_name()
86 for (i = 0; i < pctl->nfunctions; i++) { in sunxi_pinctrl_find_function_by_name()
98 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, in sunxi_pinctrl_desc_find_function_by_name() argument
104 for (i = 0; i < pctl->desc->npins; i++) { in sunxi_pinctrl_desc_find_function_by_name()
105 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; in sunxi_pinctrl_desc_find_function_by_name()
113 func->variant & pctl->variant)) in sunxi_pinctrl_desc_find_function_by_name()
125 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, in sunxi_pinctrl_desc_find_function_by_pin() argument
131 for (i = 0; i < pctl->desc->npins; i++) { in sunxi_pinctrl_desc_find_function_by_pin()
132 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; in sunxi_pinctrl_desc_find_function_by_pin()
151 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pctrl_get_groups_count() local
153 return pctl->ngroups; in sunxi_pctrl_get_groups_count()
159 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pctrl_get_group_name() local
161 return pctl->groups[group].name; in sunxi_pctrl_get_group_name()
169 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pctrl_get_group_pins() local
171 *pins = (unsigned *)&pctl->groups[group].pin; in sunxi_pctrl_get_group_pins()
376 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pctrl_dt_node_to_map() local
388 dev_err(pctl->dev, "missing function property in node %pOFn\n", in sunxi_pctrl_dt_node_to_map()
395 dev_err(pctl->dev, "missing pins property in node %pOFn\n", in sunxi_pctrl_dt_node_to_map()
420 sunxi_pinctrl_find_group_by_name(pctl, group); in sunxi_pctrl_dt_node_to_map()
423 dev_err(pctl->dev, "unknown pin %s", group); in sunxi_pctrl_dt_node_to_map()
427 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, in sunxi_pctrl_dt_node_to_map()
430 dev_err(pctl->dev, "unsupported function %s on pin %s", in sunxi_pctrl_dt_node_to_map()
498 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, in sunxi_pinctrl_set_io_bias_cfg() argument
507 if (!pctl->desc->io_bias_cfg_variant) in sunxi_pinctrl_set_io_bias_cfg()
518 switch (pctl->desc->io_bias_cfg_variant) { in sunxi_pinctrl_set_io_bias_cfg()
535 pin -= pctl->desc->pin_base; in sunxi_pinctrl_set_io_bias_cfg()
537 reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); in sunxi_pinctrl_set_io_bias_cfg()
539 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); in sunxi_pinctrl_set_io_bias_cfg()
545 raw_spin_lock_irqsave(&pctl->lock, flags); in sunxi_pinctrl_set_io_bias_cfg()
546 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); in sunxi_pinctrl_set_io_bias_cfg()
548 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); in sunxi_pinctrl_set_io_bias_cfg()
549 raw_spin_unlock_irqrestore(&pctl->lock, flags); in sunxi_pinctrl_set_io_bias_cfg()
551 if (pctl->desc->io_bias_cfg_variant == in sunxi_pinctrl_set_io_bias_cfg()
557 raw_spin_lock_irqsave(&pctl->lock, flags); in sunxi_pinctrl_set_io_bias_cfg()
558 reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG); in sunxi_pinctrl_set_io_bias_cfg()
560 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_CTL_REG); in sunxi_pinctrl_set_io_bias_cfg()
561 raw_spin_unlock_irqrestore(&pctl->lock, flags); in sunxi_pinctrl_set_io_bias_cfg()
623 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pconf_get() local
629 pin -= pctl->desc->pin_base; in sunxi_pconf_get()
631 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask, pctl->desc->hw_type); in sunxi_pconf_get()
635 val = (readl(pctl->membase + offset) >> shift) & mask; in sunxi_pconf_get()
685 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pconf_group_get() local
686 struct sunxi_pinctrl_group *g = &pctl->groups[group]; in sunxi_pconf_group_get()
695 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pconf_set() local
697 unsigned short bank_offset = bank - pctl->desc->pin_base / in sunxi_pconf_set()
699 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; in sunxi_pconf_set()
712 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask, pctl->desc->hw_type); in sunxi_pconf_set()
750 sunxi_pinctrl_set_io_bias_cfg(pctl, pin, in sunxi_pconf_set()
771 raw_spin_lock_irqsave(&pctl->lock, flags); in sunxi_pconf_set()
772 reg = readl(pctl->membase + offset); in sunxi_pconf_set()
774 writel(reg | val << shift, pctl->membase + offset); in sunxi_pconf_set()
775 raw_spin_unlock_irqrestore(&pctl->lock, flags); in sunxi_pconf_set()
784 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pconf_group_set() local
785 struct sunxi_pinctrl_group *g = &pctl->groups[group]; in sunxi_pconf_group_set()
802 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pmx_get_funcs_cnt() local
804 return pctl->nfunctions; in sunxi_pmx_get_funcs_cnt()
810 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pmx_get_func_name() local
812 return pctl->functions[function].name; in sunxi_pmx_get_func_name()
820 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pmx_get_func_groups() local
822 *groups = pctl->functions[function].groups; in sunxi_pmx_get_func_groups()
823 *num_groups = pctl->functions[function].ngroups; in sunxi_pmx_get_func_groups()
832 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pmx_set() local
836 raw_spin_lock_irqsave(&pctl->lock, flags); in sunxi_pmx_set()
838 pin -= pctl->desc->pin_base; in sunxi_pmx_set()
839 val = readl(pctl->membase + sunxi_mux_reg(pin, pctl->desc->hw_type)); in sunxi_pmx_set()
842 pctl->membase + sunxi_mux_reg(pin, pctl->desc->hw_type)); in sunxi_pmx_set()
844 raw_spin_unlock_irqrestore(&pctl->lock, flags); in sunxi_pmx_set()
851 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pmx_set_mux() local
852 struct sunxi_pinctrl_group *g = pctl->groups + group; in sunxi_pmx_set_mux()
853 struct sunxi_pinctrl_function *func = pctl->functions + function; in sunxi_pmx_set_mux()
855 sunxi_pinctrl_desc_find_function_by_name(pctl, in sunxi_pmx_set_mux()
873 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pmx_gpio_set_direction() local
882 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); in sunxi_pmx_gpio_set_direction()
893 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pmx_request() local
895 unsigned short bank_offset = bank - pctl->desc->pin_base / in sunxi_pmx_request()
897 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; in sunxi_pmx_request()
904 dev_dbg(pctl->dev, "bank P%c regulator has been opened\n", in sunxi_pmx_request()
950 reg = regulator_get(pctl->dev, supply); in sunxi_pmx_request()
952 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n", in sunxi_pmx_request()
958 if (pctl->desc->pf_power_source_switch && bank == 5 && IS_ERR_OR_NULL(reg_op)) { in sunxi_pmx_request()
959 reg_op = regulator_get(pctl->dev, "vcc-pfo"); in sunxi_pmx_request()
961 dev_err(pctl->dev, in sunxi_pmx_request()
970 dev_err(pctl->dev, in sunxi_pmx_request()
975 if (pctl->desc->pf_power_source_switch && bank == 5) { in sunxi_pmx_request()
978 dev_err(pctl->dev, in sunxi_pmx_request()
985 if (!(pctl->desc->pf_power_source_switch && bank == 5)) in sunxi_pmx_request()
986 sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg); in sunxi_pmx_request()
1006 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in sunxi_pmx_free() local
1008 unsigned short bank_offset = bank - pctl->desc->pin_base / in sunxi_pmx_free()
1010 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; in sunxi_pmx_free()
1041 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); in sunxi_pinctrl_gpio_get() local
1042 u32 reg = sunxi_data_reg(offset, pctl->desc->hw_type); in sunxi_pinctrl_gpio_get()
1044 bool set_mux = pctl->desc->irq_read_needs_mux && in sunxi_pinctrl_gpio_get()
1050 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); in sunxi_pinctrl_gpio_get()
1052 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; in sunxi_pinctrl_gpio_get()
1055 sunxi_pmx_set(pctl->pctl_dev, pin, sunxi_pinctrl_hw_info[pctl->desc->hw_type].irq_mux_val); in sunxi_pinctrl_gpio_get()
1063 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); in sunxi_pinctrl_gpio_set() local
1064 u32 reg = sunxi_data_reg(offset, pctl->desc->hw_type); in sunxi_pinctrl_gpio_set()
1069 raw_spin_lock_irqsave(&pctl->lock, flags); in sunxi_pinctrl_gpio_set()
1071 regval = readl(pctl->membase + reg); in sunxi_pinctrl_gpio_set()
1078 writel(regval, pctl->membase + reg); in sunxi_pinctrl_gpio_set()
1080 raw_spin_unlock_irqrestore(&pctl->lock, flags); in sunxi_pinctrl_gpio_set()
1110 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); in sunxi_pinctrl_gpio_to_irq() local
1112 unsigned pinnum = pctl->desc->pin_base + offset; in sunxi_pinctrl_gpio_to_irq()
1118 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); in sunxi_pinctrl_gpio_to_irq()
1127 return irq_find_mapping(pctl->domain, irqnum); in sunxi_pinctrl_gpio_to_irq()
1132 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); in sunxi_pinctrl_irq_request_resources() local
1136 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, in sunxi_pinctrl_irq_request_resources()
1137 pctl->irq_array[d->hwirq], "irq"); in sunxi_pinctrl_irq_request_resources()
1141 ret = gpiochip_lock_as_irq(pctl->chip, in sunxi_pinctrl_irq_request_resources()
1142 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); in sunxi_pinctrl_irq_request_resources()
1144 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", in sunxi_pinctrl_irq_request_resources()
1150 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); in sunxi_pinctrl_irq_request_resources()
1157 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); in sunxi_pinctrl_irq_release_resources() local
1159 gpiochip_unlock_as_irq(pctl->chip, in sunxi_pinctrl_irq_release_resources()
1160 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); in sunxi_pinctrl_irq_release_resources()
1165 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); in sunxi_pinctrl_irq_set_type() local
1166 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); in sunxi_pinctrl_irq_set_type()
1192 raw_spin_lock_irqsave(&pctl->lock, flags); in sunxi_pinctrl_irq_set_type()
1201 regval = readl(pctl->membase + reg); in sunxi_pinctrl_irq_set_type()
1203 writel(regval | (mode << index), pctl->membase + reg); in sunxi_pinctrl_irq_set_type()
1205 raw_spin_unlock_irqrestore(&pctl->lock, flags); in sunxi_pinctrl_irq_set_type()
1212 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); in sunxi_pinctrl_irq_ack() local
1213 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); in sunxi_pinctrl_irq_ack()
1217 writel(1 << status_idx, pctl->membase + status_reg); in sunxi_pinctrl_irq_ack()
1222 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); in sunxi_pinctrl_irq_mask() local
1223 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); in sunxi_pinctrl_irq_mask()
1228 raw_spin_lock_irqsave(&pctl->lock, flags); in sunxi_pinctrl_irq_mask()
1231 val = readl(pctl->membase + reg); in sunxi_pinctrl_irq_mask()
1232 writel(val & ~(1 << idx), pctl->membase + reg); in sunxi_pinctrl_irq_mask()
1234 raw_spin_unlock_irqrestore(&pctl->lock, flags); in sunxi_pinctrl_irq_mask()
1239 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); in sunxi_pinctrl_irq_unmask() local
1240 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); in sunxi_pinctrl_irq_unmask()
1245 raw_spin_lock_irqsave(&pctl->lock, flags); in sunxi_pinctrl_irq_unmask()
1248 val = readl(pctl->membase + reg); in sunxi_pinctrl_irq_unmask()
1249 writel(val | (1 << idx), pctl->membase + reg); in sunxi_pinctrl_irq_unmask()
1251 raw_spin_unlock_irqrestore(&pctl->lock, flags); in sunxi_pinctrl_irq_unmask()
1262 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); in sunxi_pinctrl_irq_set_wake() local
1264 struct irq_data *bank_irq_d = irq_get_irq_data(pctl->irq[bank]); in sunxi_pinctrl_irq_set_wake()
1311 struct sunxi_pinctrl *pctl = d->host_data; in sunxi_pinctrl_irq_of_xlate() local
1319 pin = pctl->desc->pin_base + base + intspec[1]; in sunxi_pinctrl_irq_of_xlate()
1321 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); in sunxi_pinctrl_irq_of_xlate()
1339 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); in sunxi_pinctrl_irq_handler() local
1342 for (bank = 0; bank < pctl->desc->irq_banks; bank++) in sunxi_pinctrl_irq_handler()
1343 if (irq == pctl->irq[bank]) in sunxi_pinctrl_irq_handler()
1346 BUG_ON(bank == pctl->desc->irq_banks); in sunxi_pinctrl_irq_handler()
1350 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); in sunxi_pinctrl_irq_handler()
1351 val = readl(pctl->membase + reg); in sunxi_pinctrl_irq_handler()
1357 int pin_irq = irq_find_mapping(pctl->domain, in sunxi_pinctrl_irq_handler()
1366 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, in sunxi_pinctrl_add_function() argument
1369 struct sunxi_pinctrl_function *func = pctl->functions; in sunxi_pinctrl_add_function()
1383 pctl->nfunctions++; in sunxi_pinctrl_add_function()
1390 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); in sunxi_pinctrl_build_state() local
1405 pctl->groups = devm_kcalloc(&pdev->dev, in sunxi_pinctrl_build_state()
1406 pctl->desc->npins, sizeof(*pctl->groups), in sunxi_pinctrl_build_state()
1408 if (!pctl->groups) in sunxi_pinctrl_build_state()
1411 for (i = 0; i < pctl->desc->npins; i++) { in sunxi_pinctrl_build_state()
1412 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; in sunxi_pinctrl_build_state()
1413 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups; in sunxi_pinctrl_build_state()
1415 if (pin->variant && !(pctl->variant & pin->variant)) in sunxi_pinctrl_build_state()
1422 pctl->ngroups++; in sunxi_pinctrl_build_state()
1430 pctl->functions = kcalloc(pctl->ngroups * 12 + 4, in sunxi_pinctrl_build_state()
1431 sizeof(*pctl->functions), in sunxi_pinctrl_build_state()
1433 if (!pctl->functions) in sunxi_pinctrl_build_state()
1437 for (i = 0; i < pctl->desc->npins; i++) { in sunxi_pinctrl_build_state()
1438 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; in sunxi_pinctrl_build_state()
1441 if (pin->variant && !(pctl->variant & pin->variant)) in sunxi_pinctrl_build_state()
1445 if (func->variant && !(pctl->variant & func->variant)) in sunxi_pinctrl_build_state()
1451 pctl->irq_array[irqnum] = pin->pin.number; in sunxi_pinctrl_build_state()
1454 sunxi_pinctrl_add_function(pctl, func->name); in sunxi_pinctrl_build_state()
1459 ptr = krealloc(pctl->functions, in sunxi_pinctrl_build_state()
1460 pctl->nfunctions * sizeof(*pctl->functions), in sunxi_pinctrl_build_state()
1463 kfree(pctl->functions); in sunxi_pinctrl_build_state()
1464 pctl->functions = NULL; in sunxi_pinctrl_build_state()
1467 pctl->functions = ptr; in sunxi_pinctrl_build_state()
1469 for (i = 0; i < pctl->desc->npins; i++) { in sunxi_pinctrl_build_state()
1470 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; in sunxi_pinctrl_build_state()
1473 if (pin->variant && !(pctl->variant & pin->variant)) in sunxi_pinctrl_build_state()
1480 if (func->variant && !(pctl->variant & func->variant)) in sunxi_pinctrl_build_state()
1483 func_item = sunxi_pinctrl_find_function_by_name(pctl, in sunxi_pinctrl_build_state()
1486 kfree(pctl->functions); in sunxi_pinctrl_build_state()
1497 kfree(pctl->functions); in sunxi_pinctrl_build_state()
1535 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, in sunxi_pinctrl_setup_debounce() argument
1552 losc = devm_clk_get(pctl->dev, "losc"); in sunxi_pinctrl_setup_debounce()
1556 hosc = devm_clk_get(pctl->dev, "hosc"); in sunxi_pinctrl_setup_debounce()
1560 for (i = 0; i < pctl->desc->irq_banks; i++) { in sunxi_pinctrl_setup_debounce()
1590 pctl->membase + in sunxi_pinctrl_setup_debounce()
1591 sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); in sunxi_pinctrl_setup_debounce()
1604 struct sunxi_pinctrl *pctl; in sunxi_bsp_pinctrl_init_with_variant() local
1609 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); in sunxi_bsp_pinctrl_init_with_variant()
1610 if (!pctl) in sunxi_bsp_pinctrl_init_with_variant()
1612 platform_set_drvdata(pdev, pctl); in sunxi_bsp_pinctrl_init_with_variant()
1614 raw_spin_lock_init(&pctl->lock); in sunxi_bsp_pinctrl_init_with_variant()
1616 pctl->membase = devm_platform_ioremap_resource(pdev, 0); in sunxi_bsp_pinctrl_init_with_variant()
1617 if (IS_ERR(pctl->membase)) in sunxi_bsp_pinctrl_init_with_variant()
1618 return PTR_ERR(pctl->membase); in sunxi_bsp_pinctrl_init_with_variant()
1620 pctl->dev = &pdev->dev; in sunxi_bsp_pinctrl_init_with_variant()
1621 pctl->desc = desc; in sunxi_bsp_pinctrl_init_with_variant()
1622 pctl->variant = variant; in sunxi_bsp_pinctrl_init_with_variant()
1624 pctl->irq_array = devm_kcalloc(&pdev->dev, in sunxi_bsp_pinctrl_init_with_variant()
1625 IRQ_PER_BANK * pctl->desc->irq_banks, in sunxi_bsp_pinctrl_init_with_variant()
1626 sizeof(*pctl->irq_array), in sunxi_bsp_pinctrl_init_with_variant()
1628 if (!pctl->irq_array) in sunxi_bsp_pinctrl_init_with_variant()
1638 pctl->desc->npins, sizeof(*pins), in sunxi_bsp_pinctrl_init_with_variant()
1643 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) { in sunxi_bsp_pinctrl_init_with_variant()
1644 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; in sunxi_bsp_pinctrl_init_with_variant()
1646 if (pin->variant && !(pctl->variant & pin->variant)) in sunxi_bsp_pinctrl_init_with_variant()
1661 pctrl_desc->npins = pctl->ngroups; in sunxi_bsp_pinctrl_init_with_variant()
1675 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); in sunxi_bsp_pinctrl_init_with_variant()
1676 if (IS_ERR(pctl->pctl_dev)) { in sunxi_bsp_pinctrl_init_with_variant()
1678 return PTR_ERR(pctl->pctl_dev); in sunxi_bsp_pinctrl_init_with_variant()
1681 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); in sunxi_bsp_pinctrl_init_with_variant()
1682 if (!pctl->chip) in sunxi_bsp_pinctrl_init_with_variant()
1685 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; in sunxi_bsp_pinctrl_init_with_variant()
1686 pctl->chip->owner = THIS_MODULE; in sunxi_bsp_pinctrl_init_with_variant()
1687 pctl->chip->request = gpiochip_generic_request; in sunxi_bsp_pinctrl_init_with_variant()
1688 pctl->chip->free = gpiochip_generic_free; in sunxi_bsp_pinctrl_init_with_variant()
1689 pctl->chip->set_config = gpiochip_generic_config; in sunxi_bsp_pinctrl_init_with_variant()
1690 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input; in sunxi_bsp_pinctrl_init_with_variant()
1691 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output; in sunxi_bsp_pinctrl_init_with_variant()
1692 pctl->chip->get = sunxi_pinctrl_gpio_get; in sunxi_bsp_pinctrl_init_with_variant()
1693 pctl->chip->set = sunxi_pinctrl_gpio_set; in sunxi_bsp_pinctrl_init_with_variant()
1694 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate; in sunxi_bsp_pinctrl_init_with_variant()
1695 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq; in sunxi_bsp_pinctrl_init_with_variant()
1696 pctl->chip->of_gpio_n_cells = 3; in sunxi_bsp_pinctrl_init_with_variant()
1697 pctl->chip->can_sleep = false; in sunxi_bsp_pinctrl_init_with_variant()
1698 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - in sunxi_bsp_pinctrl_init_with_variant()
1699 pctl->desc->pin_base; in sunxi_bsp_pinctrl_init_with_variant()
1700 pctl->chip->label = dev_name(&pdev->dev); in sunxi_bsp_pinctrl_init_with_variant()
1701 pctl->chip->parent = &pdev->dev; in sunxi_bsp_pinctrl_init_with_variant()
1702 pctl->chip->base = pctl->desc->pin_base; in sunxi_bsp_pinctrl_init_with_variant()
1704 ret = gpiochip_add_data(pctl->chip, pctl); in sunxi_bsp_pinctrl_init_with_variant()
1708 for (i = 0; i < pctl->desc->npins; i++) { in sunxi_bsp_pinctrl_init_with_variant()
1709 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; in sunxi_bsp_pinctrl_init_with_variant()
1711 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), in sunxi_bsp_pinctrl_init_with_variant()
1712 pin->pin.number - pctl->desc->pin_base, in sunxi_bsp_pinctrl_init_with_variant()
1729 pctl->irq = devm_kcalloc(&pdev->dev, in sunxi_bsp_pinctrl_init_with_variant()
1730 pctl->desc->irq_banks, in sunxi_bsp_pinctrl_init_with_variant()
1731 sizeof(*pctl->irq), in sunxi_bsp_pinctrl_init_with_variant()
1733 if (!pctl->irq) { in sunxi_bsp_pinctrl_init_with_variant()
1738 for (i = 0; i < pctl->desc->irq_banks; i++) { in sunxi_bsp_pinctrl_init_with_variant()
1739 pctl->irq[i] = platform_get_irq(pdev, i); in sunxi_bsp_pinctrl_init_with_variant()
1740 if (pctl->irq[i] < 0) { in sunxi_bsp_pinctrl_init_with_variant()
1741 ret = pctl->irq[i]; in sunxi_bsp_pinctrl_init_with_variant()
1746 pctl->domain = irq_domain_add_linear(node, in sunxi_bsp_pinctrl_init_with_variant()
1747 pctl->desc->irq_banks * IRQ_PER_BANK, in sunxi_bsp_pinctrl_init_with_variant()
1749 pctl); in sunxi_bsp_pinctrl_init_with_variant()
1750 if (!pctl->domain) { in sunxi_bsp_pinctrl_init_with_variant()
1756 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { in sunxi_bsp_pinctrl_init_with_variant()
1757 int irqno = irq_create_mapping(pctl->domain, i); in sunxi_bsp_pinctrl_init_with_variant()
1761 irq_set_chip_data(irqno, pctl); in sunxi_bsp_pinctrl_init_with_variant()
1764 for (i = 0; i < pctl->desc->irq_banks; i++) { in sunxi_bsp_pinctrl_init_with_variant()
1766 writel(0, pctl->membase + in sunxi_bsp_pinctrl_init_with_variant()
1767 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); in sunxi_bsp_pinctrl_init_with_variant()
1769 pctl->membase + in sunxi_bsp_pinctrl_init_with_variant()
1770 sunxi_irq_status_reg_from_bank(pctl->desc, i)); in sunxi_bsp_pinctrl_init_with_variant()
1772 irq_set_chained_handler_and_data(pctl->irq[i], in sunxi_bsp_pinctrl_init_with_variant()
1774 pctl); in sunxi_bsp_pinctrl_init_with_variant()
1777 sunxi_pinctrl_setup_debounce(pctl, node); in sunxi_bsp_pinctrl_init_with_variant()
1786 gpiochip_remove(pctl->chip); in sunxi_bsp_pinctrl_init_with_variant()