194 				   struct px30_ddr_dts_config_timing *tim)  in px30_de_skew_set_2_reg()  argument
200 	memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));  in px30_de_skew_set_2_reg()
201 	memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));  in px30_de_skew_set_2_reg()
202 	memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));  in px30_de_skew_set_2_reg()
210 		tim->ca_skew[offset] &= ~(0xf << shift);  in px30_de_skew_set_2_reg()
211 		tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);  in px30_de_skew_set_2_reg()
223 		tim->cs0_skew[offset] &= ~(0xf << shift);  in px30_de_skew_set_2_reg()
224 		tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);  in px30_de_skew_set_2_reg()
236 		tim->cs1_skew[offset] &= ~(0xf << shift);  in px30_de_skew_set_2_reg()
237 		tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);  in px30_de_skew_set_2_reg()
250 				  struct rk3328_ddr_dts_config_timing *tim)  in rk3328_de_skew_setting_2_register()  argument
256 	memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));  in rk3328_de_skew_setting_2_register()
257 	memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));  in rk3328_de_skew_setting_2_register()
258 	memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));  in rk3328_de_skew_setting_2_register()
266 		tim->ca_skew[offset] &= ~(0xf << shift);  in rk3328_de_skew_setting_2_register()
267 		tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);  in rk3328_de_skew_setting_2_register()
279 		tim->cs0_skew[offset] &= ~(0xf << shift);  in rk3328_de_skew_setting_2_register()
280 		tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);  in rk3328_de_skew_setting_2_register()
292 		tim->cs1_skew[offset] &= ~(0xf << shift);  in rk3328_de_skew_setting_2_register()
293 		tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);  in rk3328_de_skew_setting_2_register()