Lines Matching refs:enable_mask
33 u32 enable_mask; member
54 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
61 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
68 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
89 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
95 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
102 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
117 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
124 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
132 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
140 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
148 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
153 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
158 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
163 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
168 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
173 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
178 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
183 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
188 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
193 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
198 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
203 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
254 v |= clk->enable_mask; in __clk_enable()
285 v &= ~clk->enable_mask; in __clk_disable()
345 div_bit = clk->enable_mask >> 15; in set_keytchclk_rate()