69 	struct eeh_pe *pe;  in pnv_eeh_ei_write()  local
90 	pe = eeh_pe_get(hose, pe_no);  in pnv_eeh_ei_write()
91 	if (!pe)  in pnv_eeh_ei_write()
95 	ret = eeh_ops->err_inject(pe, type, func, addr, mask);  in pnv_eeh_ei_write()
338 	if (!edev || edev->pe)  in pnv_eeh_probe()
411 		edev->pe->state |= EEH_PE_CFG_RESTRICTED;  in pnv_eeh_probe()
419 	if (!(edev->pe->state & EEH_PE_PRI_BUS)) {  in pnv_eeh_probe()
420 		edev->pe->bus = pci_find_bus(hose->global_number,  in pnv_eeh_probe()
422 		if (edev->pe->bus)  in pnv_eeh_probe()
423 			edev->pe->state |= EEH_PE_PRI_BUS;  in pnv_eeh_probe()
453 static int pnv_eeh_set_option(struct eeh_pe *pe, int option)  in pnv_eeh_set_option()  argument
455 	struct pci_controller *hose = pe->phb;  in pnv_eeh_set_option()
484 			phb->freeze_pe(phb, pe->addr);  in pnv_eeh_set_option()
488 		rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);  in pnv_eeh_set_option()
492 				pe->addr);  in pnv_eeh_set_option()
501 		return phb->unfreeze_pe(phb, pe->addr, opt);  in pnv_eeh_set_option()
503 	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);  in pnv_eeh_set_option()
507 			pe->addr);  in pnv_eeh_set_option()
514 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)  in pnv_eeh_get_phb_diag()  argument
516 	struct pnv_phb *phb = pe->phb->private_data;  in pnv_eeh_get_phb_diag()
519 	rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,  in pnv_eeh_get_phb_diag()
523 			__func__, rc, pe->phb->global_number);  in pnv_eeh_get_phb_diag()
526 static int pnv_eeh_get_phb_state(struct eeh_pe *pe)  in pnv_eeh_get_phb_state()  argument
528 	struct pnv_phb *phb = pe->phb->private_data;  in pnv_eeh_get_phb_state()
535 					pe->addr,  in pnv_eeh_get_phb_state()
554 	} else if (!(pe->state & EEH_PE_ISOLATED)) {  in pnv_eeh_get_phb_state()
555 		eeh_pe_mark_isolated(pe);  in pnv_eeh_get_phb_state()
556 		pnv_eeh_get_phb_diag(pe);  in pnv_eeh_get_phb_state()
559 			pnv_pci_dump_phb_diag_data(pe->phb, pe->data);  in pnv_eeh_get_phb_state()
565 static int pnv_eeh_get_pe_state(struct eeh_pe *pe)  in pnv_eeh_get_pe_state()  argument
567 	struct pnv_phb *phb = pe->phb->private_data;  in pnv_eeh_get_pe_state()
579 	if (pe->state & EEH_PE_RESET) {  in pnv_eeh_get_pe_state()
592 		fstate = phb->get_pe_state(phb, pe->addr);  in pnv_eeh_get_pe_state()
595 						pe->addr,  in pnv_eeh_get_pe_state()
602 				pe->addr);  in pnv_eeh_get_pe_state()
639 			pe->addr, fstate);  in pnv_eeh_get_pe_state()
653 	    !(pe->state & EEH_PE_ISOLATED)) {  in pnv_eeh_get_pe_state()
655 			phb->freeze_pe(phb, pe->addr);  in pnv_eeh_get_pe_state()
657 		eeh_pe_mark_isolated(pe);  in pnv_eeh_get_pe_state()
658 		pnv_eeh_get_phb_diag(pe);  in pnv_eeh_get_pe_state()
661 			pnv_pci_dump_phb_diag_data(pe->phb, pe->data);  in pnv_eeh_get_pe_state()
677 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)  in pnv_eeh_get_state()  argument
681 	if (pe->type & EEH_PE_PHB)  in pnv_eeh_get_state()
682 		ret = pnv_eeh_get_phb_state(pe);  in pnv_eeh_get_state()
684 		ret = pnv_eeh_get_pe_state(pe);  in pnv_eeh_get_state()
1003 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)  in pnv_eeh_reset_vf_pe()  argument
1010 	edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);  in pnv_eeh_reset_vf_pe()
1034 static int pnv_eeh_reset(struct eeh_pe *pe, int option)  in pnv_eeh_reset()  argument
1036 	struct pci_controller *hose = pe->phb;  in pnv_eeh_reset()
1055 	if (pe->type & EEH_PE_PHB)  in pnv_eeh_reset()
1079 	if (pe->type & EEH_PE_VF)  in pnv_eeh_reset()
1080 		return pnv_eeh_reset_vf_pe(pe, option);  in pnv_eeh_reset()
1082 	bus = eeh_pe_bus_get(pe);  in pnv_eeh_reset()
1085 			__func__, pe->phb->global_number, pe->addr);  in pnv_eeh_reset()
1132 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,  in pnv_eeh_get_log()  argument
1136 		pnv_pci_dump_phb_diag_data(pe->phb, pe->data);  in pnv_eeh_get_log()
1149 static int pnv_eeh_configure_bridge(struct eeh_pe *pe)  in pnv_eeh_configure_bridge()  argument
1166 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,  in pnv_eeh_err_inject()  argument
1169 	struct pci_controller *hose = pe->phb;  in pnv_eeh_err_inject()
1195 	rc = opal_pci_err_inject(phb->opal_id, pe->addr,  in pnv_eeh_err_inject()
1201 			hose->global_number, pe->addr);  in pnv_eeh_err_inject()
1212 	if (!edev || !edev->pe)  in pnv_eeh_cfg_blocked()
1220 	if (edev->physfn && (edev->pe->state & EEH_PE_RESET))  in pnv_eeh_cfg_blocked()
1223 	if (edev->pe->state & EEH_PE_CFG_BLOCKED)  in pnv_eeh_cfg_blocked()
1341 			  u16 pe_no, struct eeh_pe **pe)  in pnv_eeh_get_pe()  argument
1366 	*pe = dev_pe;  in pnv_eeh_get_pe()
1385 		*pe = dev_pe;  in pnv_eeh_get_pe()
1406 static int pnv_eeh_next_error(struct eeh_pe **pe)  in pnv_eeh_next_error()  argument
1474 				*pe = phb_pe;  in pnv_eeh_next_error()
1482 				*pe = phb_pe;  in pnv_eeh_next_error()
1505 				be64_to_cpu(frozen_pe_no), pe)) {  in pnv_eeh_next_error()
1523 			} else if ((*pe)->state & EEH_PE_ISOLATED ||  in pnv_eeh_next_error()
1524 				   eeh_pe_passed(*pe)) {  in pnv_eeh_next_error()
1529 				       (*pe)->addr,  in pnv_eeh_next_error()
1530 					(*pe)->phb->global_number);  in pnv_eeh_next_error()
1533 				       eeh_pe_loc_get(*pe),  in pnv_eeh_next_error()
1553 		    !((*pe)->state & EEH_PE_ISOLATED)) {  in pnv_eeh_next_error()
1554 			eeh_pe_mark_isolated(*pe);  in pnv_eeh_next_error()
1555 			pnv_eeh_get_phb_diag(*pe);  in pnv_eeh_next_error()
1558 				pnv_pci_dump_phb_diag_data((*pe)->phb,  in pnv_eeh_next_error()
1559 							   (*pe)->data);  in pnv_eeh_next_error()
1567 			parent_pe = (*pe)->parent;  in pnv_eeh_next_error()
1576 					*pe = parent_pe;  in pnv_eeh_next_error()
1583 			eeh_pe_mark_isolated(*pe);  in pnv_eeh_next_error()