473 	void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];  in pdc_read_counter()  local
479 	bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;  in pdc_read_counter()
480 	bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;  in pdc_read_counter()
483 	bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;  in pdc_read_counter()
484 	bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;  in pdc_read_counter()
514 	void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];  in pdc_adjust_pll()  local
533 	pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);  in pdc_adjust_pll()
573 	iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);  in pdc_adjust_pll()
574 	ioread16(mmio_base + PDC_PLL_CTL); /* flush */  in pdc_adjust_pll()
584 	pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);  in pdc_adjust_pll()
600 	void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];  in pdc_detect_pll_input_clock()  local
607 	scr = ioread32(mmio_base + PDC_SYS_CTL);  in pdc_detect_pll_input_clock()
609 	iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);  in pdc_detect_pll_input_clock()
610 	ioread32(mmio_base + PDC_SYS_CTL); /* flush */  in pdc_detect_pll_input_clock()
624 	scr = ioread32(mmio_base + PDC_SYS_CTL);  in pdc_detect_pll_input_clock()
626 	iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);  in pdc_detect_pll_input_clock()
627 	ioread32(mmio_base + PDC_SYS_CTL); /* flush */  in pdc_detect_pll_input_clock()
705 	void __iomem *mmio_base;  in pdc2027x_init_one()  local
729 	mmio_base = host->iomap[PDC_MMIO_BAR];  in pdc2027x_init_one()
734 		pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);  in pdc2027x_init_one()
735 		ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];  in pdc2027x_init_one()