Lines Matching refs:pll
161 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
167 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
169 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
174 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
189 #define wait_for_pll_enable_active(pll) \ argument
190 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
192 #define wait_for_pll_enable_lock(pll) \ argument
193 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
195 #define wait_for_pll_disable(pll) \ argument
196 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
198 #define wait_for_pll_offline(pll) \ argument
199 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
201 #define wait_for_pll_update(pll) \ argument
202 wait_for_pll(pll, PLL_UPDATE, 1, "update")
204 #define wait_for_pll_update_ack_set(pll) \ argument
205 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
207 #define wait_for_pll_update_ack_clear(pll) \ argument
208 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
210 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_alpha_pll_configure() argument
215 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
216 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
217 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
219 if (pll_has_64bit_config(pll)) in clk_alpha_pll_configure()
220 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_alpha_pll_configure()
223 if (pll_alpha_width(pll) > 32) in clk_alpha_pll_configure()
224 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
244 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_alpha_pll_configure()
246 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
247 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_alpha_pll_configure()
254 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_enable() local
257 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
263 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
266 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
273 return wait_for_pll_enable_active(pll); in clk_alpha_pll_hwfsm_enable()
279 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_disable() local
282 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
286 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
287 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
292 ret = wait_for_pll_offline(pll); in clk_alpha_pll_hwfsm_disable()
298 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
303 wait_for_pll_disable(pll); in clk_alpha_pll_hwfsm_disable()
309 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in pll_is_enabled() local
312 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
332 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_enable() local
336 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
345 return wait_for_pll_enable_active(pll); in clk_alpha_pll_enable()
352 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
364 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
369 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_enable()
373 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
384 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_disable() local
387 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
398 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
405 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
443 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) in alpha_pll_find_vco() argument
445 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
446 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
460 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_recalc_rate() local
461 u32 alpha_width = pll_alpha_width(pll); in clk_alpha_pll_recalc_rate()
463 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_alpha_pll_recalc_rate()
465 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_recalc_rate()
467 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); in clk_alpha_pll_recalc_rate()
469 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
484 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) in __clk_alpha_pll_update_latch() argument
489 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
492 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
506 ret = wait_for_pll_update_ack_set(pll); in __clk_alpha_pll_update_latch()
510 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
512 ret = wait_for_pll_update(pll); in __clk_alpha_pll_update_latch()
517 ret = wait_for_pll_update_ack_clear(pll); in __clk_alpha_pll_update_latch()
527 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, in clk_alpha_pll_update_latch() argument
530 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
531 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
534 return __clk_alpha_pll_update_latch(pll); in clk_alpha_pll_update_latch()
541 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __clk_alpha_pll_set_rate() local
543 u32 l, alpha_width = pll_alpha_width(pll); in __clk_alpha_pll_set_rate()
547 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
548 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
554 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __clk_alpha_pll_set_rate()
560 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); in __clk_alpha_pll_set_rate()
562 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __clk_alpha_pll_set_rate()
565 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
570 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
573 return clk_alpha_pll_update_latch(pll, is_enabled); in __clk_alpha_pll_set_rate()
593 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_round_rate() local
594 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_round_rate()
599 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_alpha_pll_round_rate()
602 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_round_rate()
603 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_round_rate()
659 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_recalc_rate() local
662 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_huayra_recalc_rate()
663 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_recalc_rate()
666 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
712 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_set_rate() local
717 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
720 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
733 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
736 return wait_for_pll_enable_lock(pll); in alpha_pll_huayra_set_rate()
739 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
740 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
743 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
746 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
760 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, in trion_pll_is_enabled() argument
766 ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval); in trion_pll_is_enabled()
767 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval); in trion_pll_is_enabled()
776 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_is_enabled() local
778 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
783 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_enable() local
784 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
788 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_enable()
797 return wait_for_pll_enable_active(pll); in clk_trion_pll_enable()
801 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_trion_pll_enable()
803 ret = wait_for_pll_enable_lock(pll); in clk_trion_pll_enable()
808 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_enable()
814 return regmap_update_bits(regmap, PLL_MODE(pll), in clk_trion_pll_enable()
820 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_disable() local
821 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
825 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_disable()
836 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
841 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_disable()
847 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_disable()
848 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
854 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_recalc_rate() local
855 u32 l, frac, alpha_width = pll_alpha_width(pll); in clk_trion_pll_recalc_rate()
857 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_trion_pll_recalc_rate()
858 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); in clk_trion_pll_recalc_rate()
913 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_recalc_rate() local
916 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_recalc_rate()
919 ctl &= PLL_POST_DIV_MASK(pll); in clk_alpha_pll_postdiv_recalc_rate()
944 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_rate() local
947 if (pll->width == 2) in clk_alpha_pll_postdiv_round_rate()
953 pll->width, CLK_DIVIDER_POWER_OF_TWO); in clk_alpha_pll_postdiv_round_rate()
960 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_ro_rate() local
963 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_round_ro_rate()
966 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_round_ro_rate()
978 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_set_rate() local
984 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
985 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_alpha_pll_postdiv_set_rate()
1002 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_fabia_pll_configure() argument
1008 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1011 regmap_write(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1014 regmap_write(regmap, PLL_CONFIG_CTL(pll), in clk_fabia_pll_configure()
1018 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_fabia_pll_configure()
1022 regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_fabia_pll_configure()
1025 regmap_write(regmap, PLL_USER_CTL_U(pll), in clk_fabia_pll_configure()
1029 regmap_write(regmap, PLL_TEST_CTL(pll), in clk_fabia_pll_configure()
1033 regmap_write(regmap, PLL_TEST_CTL_U(pll), in clk_fabia_pll_configure()
1039 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_fabia_pll_configure()
1042 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_fabia_pll_configure()
1045 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1052 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_enable() local
1054 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1056 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_enable()
1065 return wait_for_pll_enable_active(pll); in alpha_pll_fabia_enable()
1068 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in alpha_pll_fabia_enable()
1076 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1080 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_enable()
1084 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1089 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_fabia_enable()
1093 ret = wait_for_pll_enable_lock(pll); in alpha_pll_fabia_enable()
1097 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in alpha_pll_fabia_enable()
1102 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
1109 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_disable() local
1111 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1113 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_disable()
1123 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_disable()
1128 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_fabia_disable()
1133 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_disable()
1139 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_recalc_rate() local
1140 u32 l, frac, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_recalc_rate()
1142 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_fabia_recalc_rate()
1143 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); in alpha_pll_fabia_recalc_rate()
1151 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_set_rate() local
1152 u32 l, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_set_rate()
1168 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1169 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1171 return __clk_alpha_pll_update_latch(pll); in alpha_pll_fabia_set_rate()
1176 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_prepare() local
1180 u32 cal_l, val, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_prepare()
1186 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1194 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1200 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1201 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1217 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1254 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_recalc_rate() local
1258 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1262 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1263 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1265 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1266 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1267 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1278 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_recalc_rate() local
1279 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1282 regmap_read(regmap, PLL_USER_CTL(pll), &val); in clk_trion_pll_postdiv_recalc_rate()
1284 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1285 val &= PLL_POST_DIV_MASK(pll); in clk_trion_pll_postdiv_recalc_rate()
1287 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1288 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1289 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1301 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_round_rate() local
1303 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1304 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_round_rate()
1311 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_set_rate() local
1312 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1316 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1317 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1318 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1323 return regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_postdiv_set_rate()
1324 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_trion_pll_postdiv_set_rate()
1338 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_round_rate() local
1340 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1341 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_round_rate()
1347 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_set_rate() local
1354 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1362 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1363 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1364 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1369 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1370 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1371 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1388 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_trion_pll_configure() argument
1392 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1394 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_trion_pll_configure()
1397 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1400 regmap_write(regmap, PLL_CONFIG_CTL(pll), in clk_trion_pll_configure()
1404 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_trion_pll_configure()
1408 regmap_write(regmap, PLL_CONFIG_CTL_U1(pll), in clk_trion_pll_configure()
1412 regmap_write(regmap, PLL_USER_CTL(pll), in clk_trion_pll_configure()
1416 regmap_write(regmap, PLL_USER_CTL_U(pll), in clk_trion_pll_configure()
1420 regmap_write(regmap, PLL_USER_CTL_U1(pll), in clk_trion_pll_configure()
1424 regmap_write(regmap, PLL_TEST_CTL(pll), in clk_trion_pll_configure()
1428 regmap_write(regmap, PLL_TEST_CTL_U(pll), in clk_trion_pll_configure()
1432 regmap_write(regmap, PLL_TEST_CTL_U1(pll), in clk_trion_pll_configure()
1435 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_trion_pll_configure()
1439 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_configure()
1442 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_configure()
1445 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
1455 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_prepare() local
1460 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), ®val); in __alpha_pll_trion_prepare()
1485 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_trion_set_rate() local
1487 u32 regval, l, alpha_width = pll_alpha_width(pll); in alpha_pll_trion_set_rate()
1502 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_trion_set_rate()
1503 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_trion_set_rate()
1506 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in alpha_pll_trion_set_rate()
1513 regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val); in alpha_pll_trion_set_rate()
1520 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in alpha_pll_trion_set_rate()
1526 ret = wait_for_pll_enable_lock(pll); in alpha_pll_trion_set_rate()