51 			    struct rockchip_clk_pll *pll, unsigned long rate)  in rockchip_get_pll_settings()  argument
53 	const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;  in rockchip_get_pll_settings()
56 	for (i = 0; i < pll->rate_count; i++) {  in rockchip_get_pll_settings()
67 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_pll_round_rate()  local
68 	const struct rockchip_pll_rate_table *rate_table = pll->rate_table;  in rockchip_pll_round_rate()
72 	for (i = 0; i < pll->rate_count; i++) {  in rockchip_pll_round_rate()
86 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)  in rockchip_pll_wait_lock()  argument
88 	struct regmap *grf = pll->ctx->grf;  in rockchip_pll_wait_lock()
92 	ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,  in rockchip_pll_wait_lock()
93 				       val & BIT(pll->lock_shift), 0, 1000);  in rockchip_pll_wait_lock()
120 static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)  in rockchip_rk3036_pll_wait_lock()  argument
129 	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),  in rockchip_rk3036_pll_wait_lock()
139 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,  in rockchip_rk3036_pll_get_params()  argument
144 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));  in rockchip_rk3036_pll_get_params()
150 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_get_params()
158 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));  in rockchip_rk3036_pll_get_params()
166 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_recalc_rate()  local
170 	rockchip_rk3036_pll_get_params(pll, &cur);  in rockchip_rk3036_pll_recalc_rate()
189 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,  in rockchip_rk3036_pll_set_params()  argument
192 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;  in rockchip_rk3036_pll_set_params()
193 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3036_pll_set_params()
204 	rockchip_rk3036_pll_get_params(pll, &cur);  in rockchip_rk3036_pll_set_params()
218 		       pll->reg_base + RK3036_PLLCON(0));  in rockchip_rk3036_pll_set_params()
226 		       pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_set_params()
229 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));  in rockchip_rk3036_pll_set_params()
232 	writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));  in rockchip_rk3036_pll_set_params()
235 	ret = rockchip_rk3036_pll_wait_lock(pll);  in rockchip_rk3036_pll_set_params()
239 		rockchip_rk3036_pll_set_params(pll, &cur);  in rockchip_rk3036_pll_set_params()
251 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_set_rate()  local
258 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3036_pll_set_rate()
265 	return rockchip_rk3036_pll_set_params(pll, rate);  in rockchip_rk3036_pll_set_rate()
270 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_enable()  local
273 	       pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_enable()
274 	rockchip_rk3036_pll_wait_lock(pll);  in rockchip_rk3036_pll_enable()
281 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_disable()  local
285 	       pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_disable()
290 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_is_enabled()  local
291 	u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_is_enabled()
298 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_init()  local
303 	if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))  in rockchip_rk3036_pll_init()
307 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3036_pll_init()
313 	rockchip_rk3036_pll_get_params(pll, &cur);  in rockchip_rk3036_pll_init()
338 		rockchip_rk3036_pll_set_params(pll, rate);  in rockchip_rk3036_pll_init()
380 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,  in rockchip_rk3066_pll_get_params()  argument
385 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));  in rockchip_rk3066_pll_get_params()
391 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));  in rockchip_rk3066_pll_get_params()
395 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));  in rockchip_rk3066_pll_get_params()
403 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_recalc_rate()  local
408 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_recalc_rate()
415 	rockchip_rk3066_pll_get_params(pll, &cur);  in rockchip_rk3066_pll_recalc_rate()
424 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,  in rockchip_rk3066_pll_set_params()  argument
427 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;  in rockchip_rk3066_pll_set_params()
428 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3066_pll_set_params()
437 	rockchip_rk3066_pll_get_params(pll, &cur);  in rockchip_rk3066_pll_set_params()
448 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_set_params()
455 	       pll->reg_base + RK3066_PLLCON(0));  in rockchip_rk3066_pll_set_params()
459 		       pll->reg_base + RK3066_PLLCON(1));  in rockchip_rk3066_pll_set_params()
462 		       pll->reg_base + RK3066_PLLCON(2));  in rockchip_rk3066_pll_set_params()
466 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_set_params()
470 	ret = rockchip_pll_wait_lock(pll);  in rockchip_rk3066_pll_set_params()
474 		rockchip_rk3066_pll_set_params(pll, &cur);  in rockchip_rk3066_pll_set_params()
486 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_set_rate()  local
493 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3066_pll_set_rate()
500 	return rockchip_rk3066_pll_set_params(pll, rate);  in rockchip_rk3066_pll_set_rate()
505 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_enable()  local
508 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_enable()
509 	rockchip_pll_wait_lock(pll);  in rockchip_rk3066_pll_enable()
516 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_disable()  local
520 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_disable()
525 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_is_enabled()  local
526 	u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_is_enabled()
533 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_init()  local
538 	if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))  in rockchip_rk3066_pll_init()
542 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3066_pll_init()
548 	rockchip_rk3066_pll_get_params(pll, &cur);  in rockchip_rk3066_pll_init()
557 		rockchip_rk3066_pll_set_params(pll, rate);  in rockchip_rk3066_pll_init()
600 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)  in rockchip_rk3399_pll_wait_lock()  argument
609 	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),  in rockchip_rk3399_pll_wait_lock()
619 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,  in rockchip_rk3399_pll_get_params()  argument
624 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));  in rockchip_rk3399_pll_get_params()
628 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3399_pll_get_params()
636 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_get_params()
640 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_get_params()
648 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_recalc_rate()  local
652 	rockchip_rk3399_pll_get_params(pll, &cur);  in rockchip_rk3399_pll_recalc_rate()
671 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,  in rockchip_rk3399_pll_set_params()  argument
674 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;  in rockchip_rk3399_pll_set_params()
675 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3399_pll_set_params()
686 	rockchip_rk3399_pll_get_params(pll, &cur);  in rockchip_rk3399_pll_set_params()
698 		       pll->reg_base + RK3399_PLLCON(0));  in rockchip_rk3399_pll_set_params()
706 		       pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3399_pll_set_params()
709 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_set_params()
712 	writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_set_params()
716 		       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_set_params()
719 	ret = rockchip_rk3399_pll_wait_lock(pll);  in rockchip_rk3399_pll_set_params()
723 		rockchip_rk3399_pll_set_params(pll, &cur);  in rockchip_rk3399_pll_set_params()
735 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_set_rate()  local
742 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3399_pll_set_rate()
749 	return rockchip_rk3399_pll_set_params(pll, rate);  in rockchip_rk3399_pll_set_rate()
754 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_enable()  local
757 	       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_enable()
758 	rockchip_rk3399_pll_wait_lock(pll);  in rockchip_rk3399_pll_enable()
765 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_disable()  local
769 	       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_disable()
774 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_is_enabled()  local
775 	u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_is_enabled()
782 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_init()  local
787 	if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))  in rockchip_rk3399_pll_init()
791 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3399_pll_init()
797 	rockchip_rk3399_pll_get_params(pll, &cur);  in rockchip_rk3399_pll_init()
822 		rockchip_rk3399_pll_set_params(pll, rate);  in rockchip_rk3399_pll_init()
859 	struct rockchip_clk_pll *pll;  in rockchip_clk_register_pll()  local
873 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in rockchip_clk_register_pll()
874 	if (!pll)  in rockchip_clk_register_pll()
878 	pll->pll_mux_ops = &clk_mux_ops;  in rockchip_clk_register_pll()
879 	pll_mux = &pll->pll_mux;  in rockchip_clk_register_pll()
903 	init.ops = pll->pll_mux_ops;  in rockchip_clk_register_pll()
930 		pll->rate_count = len;  in rockchip_clk_register_pll()
931 		pll->rate_table = kmemdup(rate_table,  in rockchip_clk_register_pll()
932 					pll->rate_count *  in rockchip_clk_register_pll()
935 		WARN(!pll->rate_table,  in rockchip_clk_register_pll()
943 		if (!pll->rate_table)  in rockchip_clk_register_pll()
949 		if (!pll->rate_table || IS_ERR(ctx->grf))  in rockchip_clk_register_pll()
955 		if (!pll->rate_table)  in rockchip_clk_register_pll()
965 	pll->hw.init = &init;  in rockchip_clk_register_pll()
966 	pll->type = pll_type;  in rockchip_clk_register_pll()
967 	pll->reg_base = ctx->reg_base + con_offset;  in rockchip_clk_register_pll()
968 	pll->lock_offset = grf_lock_offset;  in rockchip_clk_register_pll()
969 	pll->lock_shift = lock_shift;  in rockchip_clk_register_pll()
970 	pll->flags = clk_pll_flags;  in rockchip_clk_register_pll()
971 	pll->lock = &ctx->lock;  in rockchip_clk_register_pll()
972 	pll->ctx = ctx;  in rockchip_clk_register_pll()
974 	pll_clk = clk_register(NULL, &pll->hw);  in rockchip_clk_register_pll()
984 	kfree(pll->rate_table);  in rockchip_clk_register_pll()
988 	kfree(pll);  in rockchip_clk_register_pll()