68 struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)  in s10_register_gate()  argument
73 	const char *parent_name = clks->parent_name;  in s10_register_gate()
79 	socfpga_clk->hw.reg = regbase + clks->gate_reg;  in s10_register_gate()
80 	socfpga_clk->hw.bit_idx = clks->gate_idx;  in s10_register_gate()
85 	socfpga_clk->fixed_div = clks->fixed_div;  in s10_register_gate()
87 	if (clks->div_reg)  in s10_register_gate()
88 		socfpga_clk->div_reg = regbase + clks->div_reg;  in s10_register_gate()
92 	socfpga_clk->width = clks->div_width;  in s10_register_gate()
93 	socfpga_clk->shift = clks->div_offset;  in s10_register_gate()
95 	if (clks->bypass_reg)  in s10_register_gate()
96 		socfpga_clk->bypass_reg = regbase + clks->bypass_reg;  in s10_register_gate()
99 	socfpga_clk->bypass_shift = clks->bypass_shift;  in s10_register_gate()
101 	if (streq(clks->name, "cs_pdbg_clk"))  in s10_register_gate()
106 	init.name = clks->name;  in s10_register_gate()
107 	init.flags = clks->flags;  in s10_register_gate()
109 	init.num_parents = clks->num_parents;  in s10_register_gate()
112 		init.parent_data = clks->parent_data;  in s10_register_gate()