90 	struct tegra_clk_emc *tegra;  in emc_recalc_rate()  local
93 	tegra = container_of(hw, struct tegra_clk_emc, hw);  in emc_recalc_rate()
101 	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_recalc_rate()
114 	struct tegra_clk_emc *tegra;  in emc_determine_rate()  local
119 	tegra = container_of(hw, struct tegra_clk_emc, hw);  in emc_determine_rate()
121 	for (k = 0; k < tegra->num_timings; k++) {  in emc_determine_rate()
122 		if (tegra->timings[k].ram_code == ram_code)  in emc_determine_rate()
126 	for (t = k; t < tegra->num_timings; t++) {  in emc_determine_rate()
127 		if (tegra->timings[t].ram_code != ram_code)  in emc_determine_rate()
132 		timing = tegra->timings + i;  in emc_determine_rate()
139 			req->rate = tegra->timings[i - 1].rate;  in emc_determine_rate()
161 	struct tegra_clk_emc *tegra;  in emc_get_parent()  local
164 	tegra = container_of(hw, struct tegra_clk_emc, hw);  in emc_get_parent()
166 	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_get_parent()
172 static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)  in emc_ensure_emc_driver()  argument
176 	if (tegra->emc)  in emc_ensure_emc_driver()
177 		return tegra->emc;  in emc_ensure_emc_driver()
179 	if (!tegra->emc_node)  in emc_ensure_emc_driver()
182 	pdev = of_find_device_by_node(tegra->emc_node);  in emc_ensure_emc_driver()
189 	of_node_put(tegra->emc_node);  in emc_ensure_emc_driver()
190 	tegra->emc_node = NULL;  in emc_ensure_emc_driver()
192 	tegra->emc = platform_get_drvdata(pdev);  in emc_ensure_emc_driver()
193 	if (!tegra->emc) {  in emc_ensure_emc_driver()
199 	return tegra->emc;  in emc_ensure_emc_driver()
202 static int emc_set_timing(struct tegra_clk_emc *tegra,  in emc_set_timing()  argument
209 	struct tegra_emc *emc = emc_ensure_emc_driver(tegra);  in emc_set_timing()
217 	if (emc_get_parent(&tegra->hw) == timing->parent_index &&  in emc_set_timing()
226 	tegra->changing_timing = true;  in emc_set_timing()
249 	spin_lock_irqsave(tegra->lock, flags);  in emc_set_timing()
251 	car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_set_timing()
259 	writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);  in emc_set_timing()
261 	spin_unlock_irqrestore(tegra->lock, flags);  in emc_set_timing()
265 	clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));  in emc_set_timing()
266 	clk_disable_unprepare(tegra->prev_parent);  in emc_set_timing()
268 	tegra->prev_parent = timing->parent;  in emc_set_timing()
269 	tegra->changing_timing = false;  in emc_set_timing()
280 static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,  in get_backup_timing()  argument
287 	for (i = timing_index+1; i < tegra->num_timings; i++) {  in get_backup_timing()
288 		timing = tegra->timings + i;  in get_backup_timing()
294 		      tegra->timings[timing_index].parent_index])  in get_backup_timing()
299 		timing = tegra->timings + i;  in get_backup_timing()
305 		      tegra->timings[timing_index].parent_index])  in get_backup_timing()
315 	struct tegra_clk_emc *tegra;  in emc_set_rate()  local
320 	tegra = container_of(hw, struct tegra_clk_emc, hw);  in emc_set_rate()
330 	if (tegra->changing_timing)  in emc_set_rate()
333 	for (i = 0; i < tegra->num_timings; i++) {  in emc_set_rate()
334 		if (tegra->timings[i].rate == rate &&  in emc_set_rate()
335 		    tegra->timings[i].ram_code == ram_code) {  in emc_set_rate()
336 			timing = tegra->timings + i;  in emc_set_rate()
356 		backup_timing = get_backup_timing(tegra, i);  in emc_set_rate()
365 		err = emc_set_timing(tegra, backup_timing);  in emc_set_rate()
372 	return emc_set_timing(tegra, timing);  in emc_set_rate()
377 static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,  in load_one_timing_from_dt()  argument
433 static int load_timings_from_dt(struct tegra_clk_emc *tegra,  in load_timings_from_dt()  argument
443 	size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);  in load_timings_from_dt()
445 	tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);  in load_timings_from_dt()
446 	if (!tegra->timings)  in load_timings_from_dt()
449 	timings_ptr = tegra->timings + tegra->num_timings;  in load_timings_from_dt()
450 	tegra->num_timings += child_count;  in load_timings_from_dt()
455 		err = load_one_timing_from_dt(tegra, timing, child);  in load_timings_from_dt()
480 	struct tegra_clk_emc *tegra;  in tegra_clk_register_emc()  local
487 	tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);  in tegra_clk_register_emc()
488 	if (!tegra)  in tegra_clk_register_emc()
491 	tegra->clk_regs = base;  in tegra_clk_register_emc()
492 	tegra->lock = lock;  in tegra_clk_register_emc()
494 	tegra->num_timings = 0;  in tegra_clk_register_emc()
506 		err = load_timings_from_dt(tegra, node, node_ram_code);  in tegra_clk_register_emc()
513 	if (tegra->num_timings == 0)  in tegra_clk_register_emc()
516 	tegra->emc_node = of_parse_phandle(np,  in tegra_clk_register_emc()
518 	if (!tegra->emc_node)  in tegra_clk_register_emc()
527 	tegra->hw.init = &init;  in tegra_clk_register_emc()
529 	clk = clk_register(NULL, &tegra->hw);  in tegra_clk_register_emc()
533 	tegra->prev_parent = clk_hw_get_parent_by_index(  in tegra_clk_register_emc()
534 		&tegra->hw, emc_get_parent(&tegra->hw))->clk;  in tegra_clk_register_emc()
535 	tegra->changing_timing = false;  in tegra_clk_register_emc()