734 	if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {  in tegra210_pllcx_set_defaults()
783 	u32 val = readl_relaxed(clk_base + plla->params->base_reg);  in tegra210_plla_set_defaults()
820 	writel_relaxed(val, clk_base + plla->params->base_reg);  in tegra210_plla_set_defaults()
839 	if (readl_relaxed(clk_base + plld->params->base_reg) &  in tegra210_plld_set_defaults()
889 	u32 val = readl_relaxed(clk_base + plldss->params->base_reg);  in plldss_defaults()
940 					plldss->params->base_reg);  in plldss_defaults()
955 	writel_relaxed(val, clk_base + plldss->params->base_reg);  in plldss_defaults()
1008 	u32 val = readl_relaxed(clk_base + pllre->params->base_reg);  in tegra210_pllre_set_defaults()
1052 	writel_relaxed(val, clk_base + pllre->params->base_reg);  in tegra210_pllre_set_defaults()
1137 	if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {  in tegra210_pllx_set_defaults()
1186 	u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);  in tegra210_pllmb_set_defaults()
1247 	u32 val = readl_relaxed(clk_base + pllp->params->base_reg);  in tegra210_pllp_set_defaults()
1310 	u32 val = readl_relaxed(clk_base + pllu->base_reg);  in tegra210_pllu_set_defaults()
1401 	base = readl_relaxed(clk_base + pllx->params->base_reg) &  in tegra210_pllx_dyn_ramp()
1404 	writel_relaxed(base, clk_base + pllx->params->base_reg);  in tegra210_pllx_dyn_ramp()
1609 	.base_reg = PLLX_BASE,
1660 	.base_reg = PLLC_BASE,
1699 	.base_reg = PLLC2_BASE,
1729 	.base_reg = PLLC3_BASE,
1794 	.base_reg = PLLC4_BASE,
1848 	.base_reg = PLLM_BASE,
1875 	.base_reg = PLLMB_BASE,
1920 	.base_reg = PLLE_BASE,
1957 	.base_reg = PLLRE_BASE,
1996 	.base_reg = PLLP_BASE,
2019 	.base_reg = PLLA1_BASE,
2069 	.base_reg = PLLA_BASE,
2116 	.base_reg = PLLD_BASE,
2155 	.base_reg = PLLD2_BASE,
2199 	.base_reg = PLLDP_BASE,
2251 	.base_reg = PLLU_BASE,