Lines Matching refs:FFACTOR
396 FFACTOR(0, "clk4m", "osc24m", 1, 6, 0),
397 FFACTOR(0, "clk2m", "osc24m", 1, 12, 0),
399 FFACTOR(0, "clk1600m", "pll_cpu", 1, 1, CLK_SET_RATE_PARENT),
400 FFACTOR(0, "clk800m", "pll_cpu", 1, 2, CLK_SET_RATE_PARENT),
402 FFACTOR(0, "clk25m", "pll_mac", 1, 40, 0),
403 FFACTOR(0, "clk125m", "pll_mac", 1, 8, 0),
404 FFACTOR(0, "clk250m", "pll_mac", 1, 4, 0),
405 FFACTOR(0, "clk50m", "pll_mac", 1, 20, 0),
406 FFACTOR(0, "clk500m", "pll_mac", 1, 2, 0),
407 FFACTOR(0, "clk1000m", "pll_mac", 1, 1, 0),
408 FFACTOR(0, "clk334m", "pll_mac", 1, 3, 0),
409 FFACTOR(0, "clk167m", "pll_mac", 1, 6, 0),
411 FFACTOR(0, "clk54m_mm0", "pll_mm0", 1, 22, 0),
412 FFACTOR(0, "clk74m25", "pll_mm0", 1, 16, 0),
413 FFACTOR(0, "clk148m5", "pll_mm0", 1, 8, 0),
414 FFACTOR(0, "clk297m", "pll_mm0", 1, 4, 0),
415 FFACTOR(0, "clk594m", "pll_mm0", 1, 2, 0),
416 FFACTOR(0, "pll_mm0_1188m", "pll_mm0", 1, 1, 0),
417 FFACTOR(0, "clk396m", "pll_mm0", 1, 3, 0),
418 FFACTOR(0, "clk198m", "pll_mm0", 1, 6, 0),
419 FFACTOR(0, "clk99m", "pll_mm0", 1, 12, 0),
420 FFACTOR(0, "clk49m5", "pll_mm0", 1, 24, 0),
422 FFACTOR(0, "clk324m", "pll_mm1", 1, 4, 0),
423 FFACTOR(0, "clk648m", "pll_mm1", 1, 2, 0),
424 FFACTOR(0, "pll_mm1_1296m", "pll_mm1", 1, 1, 0),
425 FFACTOR(0, "clk216m", "pll_mm1", 1, 6, 0),
426 FFACTOR(0, "clk432m", "pll_mm1", 1, 3, 0),
427 FFACTOR(0, "clk108m", "pll_mm1", 1, 12, 0),
428 FFACTOR(0, "clk72m", "pll_mm1", 1, 18, 0),
429 FFACTOR(0, "clk27m", "pll_mm1", 1, 48, 0),
430 FFACTOR(0, "clk54m", "pll_mm1", 1, 24, 0),
432 FFACTOR(0, "pll_vga_1800m", "pll_vga", 1, 1, 0),
433 FFACTOR(0, "clk_vga", "pll_vga", 1, 1, CLK_SET_RATE_PARENT),
435 FFACTOR(0, "clk466m", "pll_ddr", 1, 2, 0),
438 FFACTOR(0, "pll_audio_1800m", "pll_audio", 1, 1, 0),
439 FFACTOR(0, "clk32k768", "pll_audio", 1, 27000, 0),
440 FFACTOR(0, "clk16m384", "pll_audio", 1, 54, 0),
441 FFACTOR(0, "clk294m", "pll_audio", 1, 3, 0),
444 FFACTOR(0, "clk240m", "pll_hsic", 1, 4, 0),
445 FFACTOR(0, "clk480m", "pll_hsic", 1, 2, 0),
446 FFACTOR(0, "clk192m", "pll_hsic", 1, 5, 0),
447 FFACTOR(0, "clk_pll_24m", "pll_hsic", 1, 40, 0),
448 FFACTOR(0, "emmc_mux_div2", "emmc_mux", 1, 2, CLK_SET_RATE_PARENT),