Lines Matching refs:qm
252 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) in hisi_zip_set_user_domain_and_cache() argument
254 void __iomem *base = qm->io_base; in hisi_zip_set_user_domain_and_cache()
282 if (qm->use_sva) { in hisi_zip_set_user_domain_and_cache()
302 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) in hisi_zip_hw_error_enable() argument
306 if (qm->ver == QM_HW_V1) { in hisi_zip_hw_error_enable()
308 qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
309 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); in hisi_zip_hw_error_enable()
314 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE); in hisi_zip_hw_error_enable()
317 writel(0x1, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); in hisi_zip_hw_error_enable()
318 writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); in hisi_zip_hw_error_enable()
320 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_hw_error_enable()
323 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
326 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_hw_error_enable()
328 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_hw_error_enable()
331 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) in hisi_zip_hw_error_disable() argument
336 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_disable()
339 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_hw_error_disable()
341 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_hw_error_disable()
348 return &hisi_zip->qm; in file_to_qm()
353 struct hisi_qm *qm = file_to_qm(file); in current_qm_read() local
355 return readl(qm->io_base + QM_DFX_MB_CNT_VF); in current_qm_read()
360 struct hisi_qm *qm = file_to_qm(file); in current_qm_write() local
364 if (val > qm->vfs_num) in current_qm_write()
369 qm->debug.curr_qm_qp_num = qm->qp_num; in current_qm_write()
371 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / qm->vfs_num; in current_qm_write()
372 if (val == qm->vfs_num) in current_qm_write()
373 qm->debug.curr_qm_qp_num = qm->ctrl_qp_num - in current_qm_write()
374 qm->qp_num - (qm->vfs_num - 1) * vfq_num; in current_qm_write()
376 qm->debug.curr_qm_qp_num = vfq_num; in current_qm_write()
379 writel(val, qm->io_base + QM_DFX_MB_CNT_VF); in current_qm_write()
380 writel(val, qm->io_base + QM_DFX_DB_CNT_VF); in current_qm_write()
383 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK); in current_qm_write()
384 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); in current_qm_write()
387 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK); in current_qm_write()
388 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); in current_qm_write()
395 struct hisi_qm *qm = file_to_qm(file); in clear_enable_read() local
397 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & in clear_enable_read()
403 struct hisi_qm *qm = file_to_qm(file); in clear_enable_write() local
409 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & in clear_enable_write()
411 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in clear_enable_write()
516 static int hisi_zip_core_debug_init(struct hisi_qm *qm) in hisi_zip_core_debug_init() argument
518 struct device *dev = &qm->pdev->dev; in hisi_zip_core_debug_init()
537 regset->base = qm->io_base + core_offsets[i]; in hisi_zip_core_debug_init()
539 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); in hisi_zip_core_debug_init()
546 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) in hisi_zip_dfx_debug_init() argument
548 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); in hisi_zip_dfx_debug_init()
554 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); in hisi_zip_dfx_debug_init()
563 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) in hisi_zip_ctrl_debug_init() argument
565 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); in hisi_zip_ctrl_debug_init()
574 qm->debug.debug_root, in hisi_zip_ctrl_debug_init()
579 return hisi_zip_core_debug_init(qm); in hisi_zip_ctrl_debug_init()
582 static int hisi_zip_debugfs_init(struct hisi_qm *qm) in hisi_zip_debugfs_init() argument
584 struct device *dev = &qm->pdev->dev; in hisi_zip_debugfs_init()
590 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; in hisi_zip_debugfs_init()
591 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; in hisi_zip_debugfs_init()
592 qm->debug.debug_root = dev_d; in hisi_zip_debugfs_init()
593 ret = hisi_qm_debug_init(qm); in hisi_zip_debugfs_init()
597 if (qm->fun_type == QM_HW_PF) { in hisi_zip_debugfs_init()
598 ret = hisi_zip_ctrl_debug_init(qm); in hisi_zip_debugfs_init()
603 hisi_zip_dfx_debug_init(qm); in hisi_zip_debugfs_init()
613 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) in hisi_zip_debug_regs_clear() argument
618 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); in hisi_zip_debug_regs_clear()
619 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); in hisi_zip_debug_regs_clear()
622 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in hisi_zip_debug_regs_clear()
625 readl(qm->io_base + core_offsets[i] + in hisi_zip_debug_regs_clear()
629 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in hisi_zip_debug_regs_clear()
631 hisi_qm_debug_regs_clear(qm); in hisi_zip_debug_regs_clear()
634 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) in hisi_zip_debugfs_exit() argument
636 debugfs_remove_recursive(qm->debug.debug_root); in hisi_zip_debugfs_exit()
638 if (qm->fun_type == QM_HW_PF) { in hisi_zip_debugfs_exit()
639 hisi_zip_debug_regs_clear(qm); in hisi_zip_debugfs_exit()
640 qm->debug.curr_qm_qp_num = 0; in hisi_zip_debugfs_exit()
644 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) in hisi_zip_log_hw_error() argument
647 struct device *dev = &qm->pdev->dev; in hisi_zip_log_hw_error()
656 err_val = readl(qm->io_base + in hisi_zip_log_hw_error()
667 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) in hisi_zip_get_hw_err_status() argument
669 return readl(qm->io_base + HZIP_CORE_INT_STATUS); in hisi_zip_get_hw_err_status()
672 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) in hisi_zip_clear_hw_err_status() argument
674 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); in hisi_zip_clear_hw_err_status()
677 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) in hisi_zip_open_axi_master_ooo() argument
681 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
684 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
687 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
690 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) in hisi_zip_close_axi_master_ooo() argument
695 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_close_axi_master_ooo()
697 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_close_axi_master_ooo()
701 qm->io_base + HZIP_CORE_INT_SET); in hisi_zip_close_axi_master_ooo()
726 struct hisi_qm *qm = &hisi_zip->qm; in hisi_zip_pf_probe_init() local
729 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); in hisi_zip_pf_probe_init()
736 if (qm->ver == QM_HW_V1) in hisi_zip_pf_probe_init()
737 qm->ctrl_qp_num = HZIP_QUEUE_NUM_V1; in hisi_zip_pf_probe_init()
739 qm->ctrl_qp_num = HZIP_QUEUE_NUM_V2; in hisi_zip_pf_probe_init()
741 qm->err_ini = &hisi_zip_err_ini; in hisi_zip_pf_probe_init()
743 hisi_zip_set_user_domain_and_cache(qm); in hisi_zip_pf_probe_init()
744 hisi_qm_dev_err_init(qm); in hisi_zip_pf_probe_init()
745 hisi_zip_debug_regs_clear(qm); in hisi_zip_pf_probe_init()
750 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) in hisi_zip_qm_init() argument
752 qm->pdev = pdev; in hisi_zip_qm_init()
753 qm->ver = pdev->revision; in hisi_zip_qm_init()
754 qm->algs = "zlib\ngzip"; in hisi_zip_qm_init()
755 qm->sqe_size = HZIP_SQE_SIZE; in hisi_zip_qm_init()
756 qm->dev_name = hisi_zip_name; in hisi_zip_qm_init()
758 qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ? in hisi_zip_qm_init()
760 if (qm->fun_type == QM_HW_PF) { in hisi_zip_qm_init()
761 qm->qp_base = HZIP_PF_DEF_Q_BASE; in hisi_zip_qm_init()
762 qm->qp_num = pf_q_num; in hisi_zip_qm_init()
763 qm->debug.curr_qm_qp_num = pf_q_num; in hisi_zip_qm_init()
764 qm->qm_list = &zip_devices; in hisi_zip_qm_init()
765 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { in hisi_zip_qm_init()
773 qm->qp_base = HZIP_PF_DEF_Q_NUM; in hisi_zip_qm_init()
774 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; in hisi_zip_qm_init()
777 return hisi_qm_init(qm); in hisi_zip_qm_init()
782 struct hisi_qm *qm = &hisi_zip->qm; in hisi_zip_probe_init() local
785 if (qm->fun_type == QM_HW_PF) { in hisi_zip_probe_init()
797 struct hisi_qm *qm; in hisi_zip_probe() local
804 qm = &hisi_zip->qm; in hisi_zip_probe()
806 ret = hisi_zip_qm_init(qm, pdev); in hisi_zip_probe()
818 ret = hisi_qm_start(qm); in hisi_zip_probe()
822 ret = hisi_zip_debugfs_init(qm); in hisi_zip_probe()
826 ret = hisi_qm_alg_register(qm, &zip_devices); in hisi_zip_probe()
832 if (qm->uacce) { in hisi_zip_probe()
833 ret = uacce_register(qm->uacce); in hisi_zip_probe()
840 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { in hisi_zip_probe()
849 hisi_qm_alg_unregister(qm, &zip_devices); in hisi_zip_probe()
852 hisi_zip_debugfs_exit(qm); in hisi_zip_probe()
853 hisi_qm_stop(qm, QM_NORMAL); in hisi_zip_probe()
856 hisi_qm_dev_err_uninit(qm); in hisi_zip_probe()
859 hisi_qm_uninit(qm); in hisi_zip_probe()
866 struct hisi_qm *qm = pci_get_drvdata(pdev); in hisi_zip_remove() local
868 hisi_qm_wait_task_finish(qm, &zip_devices); in hisi_zip_remove()
869 hisi_qm_alg_unregister(qm, &zip_devices); in hisi_zip_remove()
871 if (qm->fun_type == QM_HW_PF && qm->vfs_num) in hisi_zip_remove()
872 hisi_qm_sriov_disable(pdev, qm->is_frozen); in hisi_zip_remove()
874 hisi_zip_debugfs_exit(qm); in hisi_zip_remove()
875 hisi_qm_stop(qm, QM_NORMAL); in hisi_zip_remove()
876 hisi_qm_dev_err_uninit(qm); in hisi_zip_remove()
877 hisi_qm_uninit(qm); in hisi_zip_remove()