Lines Matching refs:cpu_to_be32
328 #define DESC_HDR_DONE cpu_to_be32(0xff000000)
329 #define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
330 #define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
331 #define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
334 #define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
335 #define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
336 #define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
337 #define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
338 #define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
339 #define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
340 #define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
341 #define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
342 #define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
343 #define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
346 #define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
347 #define DESC_HDR_MODE0_AESU_MASK cpu_to_be32(0x00600000)
348 #define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
349 #define DESC_HDR_MODE0_AESU_CTR cpu_to_be32(0x00600000)
350 #define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
351 #define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
352 #define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
353 #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
354 #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
355 #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
356 #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
357 #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
358 #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
359 #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
360 #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
361 #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
370 #define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
371 #define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
372 #define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
373 #define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
376 #define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
377 #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
378 #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
379 #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
380 #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
381 #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
382 #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
383 #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
384 #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
385 #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
400 #define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
403 #define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
406 #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
407 #define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
408 #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
409 #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)