193 	u32 cr;  in mcde_configure_extsrc()  local
198 		cr = MCDE_EXTSRC0CR;  in mcde_configure_extsrc()
202 		cr = MCDE_EXTSRC1CR;  in mcde_configure_extsrc()
206 		cr = MCDE_EXTSRC2CR;  in mcde_configure_extsrc()
210 		cr = MCDE_EXTSRC3CR;  in mcde_configure_extsrc()
214 		cr = MCDE_EXTSRC4CR;  in mcde_configure_extsrc()
218 		cr = MCDE_EXTSRC5CR;  in mcde_configure_extsrc()
222 		cr = MCDE_EXTSRC6CR;  in mcde_configure_extsrc()
226 		cr = MCDE_EXTSRC7CR;  in mcde_configure_extsrc()
230 		cr = MCDE_EXTSRC8CR;  in mcde_configure_extsrc()
234 		cr = MCDE_EXTSRC9CR;  in mcde_configure_extsrc()
328 	writel(val, mcde->regs + cr);  in mcde_configure_extsrc()
344 	u32 cr;  in mcde_configure_overlay()  local
354 		cr = MCDE_OVL0CR;  in mcde_configure_overlay()
362 		cr = MCDE_OVL1CR;  in mcde_configure_overlay()
370 		cr = MCDE_OVL2CR;  in mcde_configure_overlay()
378 		cr = MCDE_OVL3CR;  in mcde_configure_overlay()
386 		cr = MCDE_OVL4CR;  in mcde_configure_overlay()
394 		cr = MCDE_OVL5CR;  in mcde_configure_overlay()
475 	writel(val, mcde->regs + cr);  in mcde_configure_overlay()
737 	u32 cr;  in mcde_enable_fifo()  local
741 		cr = MCDE_CRA0;  in mcde_enable_fifo()
744 		cr = MCDE_CRB0;  in mcde_enable_fifo()
753 	val = readl(mcde->regs + cr);  in mcde_enable_fifo()
755 	writel(val, mcde->regs + cr);  in mcde_enable_fifo()
765 	u32 cr;  in mcde_disable_fifo()  local
769 		cr = MCDE_CRA0;  in mcde_disable_fifo()
772 		cr = MCDE_CRB0;  in mcde_disable_fifo()
781 	val = readl(mcde->regs + cr);  in mcde_disable_fifo()
783 	writel(val, mcde->regs + cr);  in mcde_disable_fifo()
791 	while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) {  in mcde_disable_fifo()