Lines Matching refs:idx
756 unsigned idx) in evergreen_cs_track_validate_texture() argument
764 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
765 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
766 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
767 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
768 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
769 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
770 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
771 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1050 unsigned idx, unsigned reg) in evergreen_packet0_check() argument
1059 idx, reg); in evergreen_packet0_check()
1064 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); in evergreen_packet0_check()
1074 unsigned idx; in evergreen_cs_parse_packet0() local
1077 idx = pkt->idx + 1; in evergreen_cs_parse_packet0()
1079 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { in evergreen_cs_parse_packet0()
1080 r = evergreen_packet0_check(p, pkt, idx, reg); in evergreen_cs_parse_packet0()
1094 static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in evergreen_cs_handle_reg() argument
1149 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1152 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1170 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1178 ib[idx] &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_handle_reg()
1180 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1188 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1189 ib[idx] |= DB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1198 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1202 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1206 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1210 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1220 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1221 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1232 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1233 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1244 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1256 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1257 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1262 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1266 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1280 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_handle_reg()
1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1291 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_handle_reg()
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1304 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1308 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1317 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; in evergreen_cs_handle_reg()
1326 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; in evergreen_cs_handle_reg()
1338 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1346 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1358 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1366 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1376 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1384 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1398 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1406 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1418 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1419 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1427 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1428 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1452 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1453 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1460 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1480 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1481 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1488 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1505 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1522 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1534 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1545 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1562 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1563 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1578 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1579 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1590 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1591 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1597 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1599 ib[idx] |= 3; in evergreen_cs_handle_reg()
1708 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1722 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1736 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1739 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_handle_reg()
1742 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_cs_handle_reg()
1778 unsigned idx; in evergreen_packet3_check() local
1786 idx = pkt->idx + 1; in evergreen_packet3_check()
1787 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1801 tmp = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
1823 ib[idx + 0] = offset; in evergreen_packet3_check()
1824 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
1867 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1869 ib[idx+0] = offset; in evergreen_packet3_check()
1870 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1902 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1904 ib[idx+0] = offset; in evergreen_packet3_check()
1905 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1929 radeon_get_ib_value(p, idx+1) + in evergreen_packet3_check()
1930 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
1932 ib[idx+1] = offset; in evergreen_packet3_check()
1933 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1949 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1960 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2025 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2026 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2065 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2079 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2102 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2103 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2105 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); in evergreen_packet3_check()
2106 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2120 command = radeon_get_ib_value(p, idx+4); in evergreen_packet3_check()
2122 info = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2155 tmp = radeon_get_ib_value(p, idx) + in evergreen_packet3_check()
2156 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
2166 ib[idx] = offset; in evergreen_packet3_check()
2167 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2193 tmp = radeon_get_ib_value(p, idx+2) + in evergreen_packet3_check()
2194 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); in evergreen_packet3_check()
2204 ib[idx+2] = offset; in evergreen_packet3_check()
2205 ib[idx+3] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2225 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in evergreen_packet3_check()
2226 radeon_get_ib_value(p, idx + 2) != 0) { in evergreen_packet3_check()
2232 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2249 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in evergreen_packet3_check()
2250 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2252 ib[idx+1] = offset & 0xfffffff8; in evergreen_packet3_check()
2253 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2271 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2272 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2274 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2275 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2293 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2294 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2296 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2297 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2309 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { in evergreen_packet3_check()
2312 r = evergreen_cs_handle_reg(p, reg, idx); in evergreen_packet3_check()
2326 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { in evergreen_packet3_check()
2329 r = evergreen_cs_handle_reg(p, reg, idx); in evergreen_packet3_check()
2352 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { in evergreen_packet3_check()
2361 ib[idx+1+(i*8)+1] |= in evergreen_packet3_check()
2369 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); in evergreen_packet3_check()
2370 ib[idx+1+(i*8)+7] |= in evergreen_packet3_check()
2381 tex_dim = ib[idx+1+(i*8)+0] & 0x7; in evergreen_packet3_check()
2382 mip_address = ib[idx+1+(i*8)+3]; in evergreen_packet3_check()
2401 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); in evergreen_packet3_check()
2404 ib[idx+1+(i*8)+2] += toffset; in evergreen_packet3_check()
2405 ib[idx+1+(i*8)+3] += moffset; in evergreen_packet3_check()
2416 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); in evergreen_packet3_check()
2417 size = radeon_get_ib_value(p, idx+1+(i*8)+1); in evergreen_packet3_check()
2421 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2425 ib[idx+1+(i*8)+0] = offset64; in evergreen_packet3_check()
2426 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in evergreen_packet3_check()
2498 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2499 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2506 ib[idx+1] = offset; in evergreen_packet3_check()
2507 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2517 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2518 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2525 ib[idx+3] = offset; in evergreen_packet3_check()
2526 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2542 offset = radeon_get_ib_value(p, idx+0); in evergreen_packet3_check()
2543 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; in evergreen_packet3_check()
2554 ib[idx+0] = offset; in evergreen_packet3_check()
2555 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2571 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2572 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2579 ib[idx+1] = offset; in evergreen_packet3_check()
2580 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2583 reg = radeon_get_ib_value(p, idx+1) << 2; in evergreen_packet3_check()
2586 reg, idx + 1); in evergreen_packet3_check()
2598 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2599 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2606 ib[idx+3] = offset; in evergreen_packet3_check()
2607 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2610 reg = radeon_get_ib_value(p, idx+3) << 2; in evergreen_packet3_check()
2613 reg, idx + 3); in evergreen_packet3_check()
2635 areg, idx); in evergreen_packet3_check()
2648 offset = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
2652 offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32; in evergreen_packet3_check()
2655 ib[idx+1] = (offset & 0xfffffffc) | swap; in evergreen_packet3_check()
2656 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2749 r = radeon_cs_packet_parse(p, &pkt, p->idx); in evergreen_cs_parse()
2755 p->idx += pkt.count + 2; in evergreen_cs_parse()
2776 } while (p->idx < p->chunk_ib->length_dw); in evergreen_cs_parse()
2803 u32 idx; in evergreen_dma_cs_parse() local
2808 if (p->idx >= ib_chunk->length_dw) { in evergreen_dma_cs_parse()
2810 p->idx, ib_chunk->length_dw); in evergreen_dma_cs_parse()
2813 idx = p->idx; in evergreen_dma_cs_parse()
2814 header = radeon_get_ib_value(p, idx); in evergreen_dma_cs_parse()
2829 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2832 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2833 p->idx += count + 7; in evergreen_dma_cs_parse()
2837 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2838 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_dma_cs_parse()
2840 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2841 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2842 p->idx += count + 3; in evergreen_dma_cs_parse()
2845 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header); in evergreen_dma_cs_parse()
2869 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2870 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2871 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2872 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2883 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2884 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2885 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2886 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2887 p->idx += 5; in evergreen_dma_cs_parse()
2892 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2894 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2896 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2898 dst_offset = radeon_get_ib_value(p, idx + 7); in evergreen_dma_cs_parse()
2899 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2900 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2901 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2904 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2905 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2906 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2907 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2909 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2911 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2923 p->idx += 9; in evergreen_dma_cs_parse()
2928 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2929 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2930 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2931 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2942 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2943 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2944 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2945 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2946 p->idx += 5; in evergreen_dma_cs_parse()
2955 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2956 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2957 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2958 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2960 p->idx += 9; in evergreen_dma_cs_parse()
2970 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2971 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2972 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2973 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; in evergreen_dma_cs_parse()
2974 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
2975 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in evergreen_dma_cs_parse()
2991 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2992 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2993 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2994 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2995 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2996 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2997 p->idx += 7; in evergreen_dma_cs_parse()
3001 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3010 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3012 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3014 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3015 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3031 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3032 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3033 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3034 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3035 p->idx += 10; in evergreen_dma_cs_parse()
3045 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3047 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3049 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3050 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3053 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3054 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3056 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3058 p->idx += 12; in evergreen_dma_cs_parse()
3063 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3072 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3074 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3076 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3077 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3093 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3094 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3095 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3096 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3097 p->idx += 10; in evergreen_dma_cs_parse()
3103 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3105 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3107 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3109 dst_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3110 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3111 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3112 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3115 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3116 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3117 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3118 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3120 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3122 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3134 p->idx += 9; in evergreen_dma_cs_parse()
3143 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3144 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3145 p->idx += 13; in evergreen_dma_cs_parse()
3150 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3159 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3161 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3163 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3164 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3180 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3181 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3182 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3183 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3184 p->idx += 10; in evergreen_dma_cs_parse()
3187 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header); in evergreen_dma_cs_parse()
3197 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3198 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in evergreen_dma_cs_parse()
3204 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3205 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()
3206 p->idx += 4; in evergreen_dma_cs_parse()
3209 p->idx += 1; in evergreen_dma_cs_parse()
3212 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_cs_parse()
3215 } while (p->idx < p->chunk_ib->length_dw); in evergreen_dma_cs_parse()
3351 u32 idx = pkt->idx + 1; in evergreen_vm_packet3_check() local
3352 u32 idx_value = ib[idx]; in evergreen_vm_packet3_check()
3409 reg = ib[idx + 5] * 4; in evergreen_vm_packet3_check()
3416 reg = ib[idx + 3] * 4; in evergreen_vm_packet3_check()
3437 command = ib[idx + 4]; in evergreen_vm_packet3_check()
3438 info = ib[idx + 1]; in evergreen_vm_packet3_check()
3475 start_reg = ib[idx + 2]; in evergreen_vm_packet3_check()
3510 areg, idx); in evergreen_vm_packet3_check()
3524 u32 idx = 0; in evergreen_ib_parse() local
3528 pkt.idx = idx; in evergreen_ib_parse()
3529 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); in evergreen_ib_parse()
3530 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); in evergreen_ib_parse()
3538 idx += 1; in evergreen_ib_parse()
3541 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); in evergreen_ib_parse()
3543 idx += pkt.count + 2; in evergreen_ib_parse()
3552 } while (idx < ib->length_dw); in evergreen_ib_parse()
3568 u32 idx = 0; in evergreen_dma_ib_parse() local
3572 header = ib->ptr[idx]; in evergreen_dma_ib_parse()
3582 idx += count + 7; in evergreen_dma_ib_parse()
3586 idx += count + 3; in evergreen_dma_ib_parse()
3589 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3597 idx += 5; in evergreen_dma_ib_parse()
3601 idx += 9; in evergreen_dma_ib_parse()
3605 idx += 5; in evergreen_dma_ib_parse()
3609 idx += 9; in evergreen_dma_ib_parse()
3613 idx += 7; in evergreen_dma_ib_parse()
3617 idx += 10; in evergreen_dma_ib_parse()
3621 idx += 12; in evergreen_dma_ib_parse()
3625 idx += 10; in evergreen_dma_ib_parse()
3629 idx += 9; in evergreen_dma_ib_parse()
3633 idx += 13; in evergreen_dma_ib_parse()
3637 idx += 10; in evergreen_dma_ib_parse()
3640 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3645 idx += 4; in evergreen_dma_ib_parse()
3648 idx += 1; in evergreen_dma_ib_parse()
3651 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_ib_parse()
3654 } while (idx < ib->length_dw); in evergreen_dma_ib_parse()