849 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r100_ring_hdp_flush()
852 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r100_ring_hdp_flush()
865 	radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  in r100_fence_ring_emit()
867 	radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));  in r100_fence_ring_emit()
870 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r100_fence_ring_emit()
874 	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));  in r100_fence_ring_emit()
876 	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));  in r100_fence_ring_emit()
951 	radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));  in r100_copy_blit()
953 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r100_copy_blit()
990 	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));  in r100_ring_start()
3670 	radeon_ring_write(ring, PACKET0(scratch, 0));  in r100_ring_test()
3697 		radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));  in r100_ring_ib_execute()
3701 	radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));  in r100_ring_ib_execute()
3725 	ib.ptr[0] = PACKET0(scratch, 0);  in r100_ib_test()