Lines Matching refs:idx
838 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx); in r600_cs_common_vline_parse()
849 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_common_vline_parse()
865 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { in r600_cs_common_vline_parse()
870 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { in r600_cs_common_vline_parse()
876 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); in r600_cs_common_vline_parse()
880 h_idx = p->idx - 2; in r600_cs_common_vline_parse()
881 p->idx += wait_reg_mem.count + 2; in r600_cs_common_vline_parse()
882 p->idx += p3reloc.count + 2; in r600_cs_common_vline_parse()
919 unsigned idx, unsigned reg) in r600_packet0_check() argument
928 idx, reg); in r600_packet0_check()
933 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); in r600_packet0_check()
943 unsigned idx; in r600_cs_parse_packet0() local
946 idx = pkt->idx + 1; in r600_cs_parse_packet0()
948 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { in r600_cs_parse_packet0()
949 r = r600_packet0_check(p, pkt, idx, reg); in r600_cs_parse_packet0()
967 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in r600_cs_check_reg() argument
976 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_cs_check_reg()
1021 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1024 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1027 track->db_depth_control = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1039 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1040 ib[idx] &= C_028010_ARRAY_MODE; in r600_cs_check_reg()
1043 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1046 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1050 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1055 track->db_depth_view = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1059 track->db_depth_size = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1060 track->db_depth_size_idx = idx; in r600_cs_check_reg()
1064 track->vgt_strmout_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1068 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1082 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1083 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1094 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in r600_cs_check_reg()
1104 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1107 track->cb_target_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1111 track->cb_shader_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1114 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); in r600_cs_check_reg()
1120 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx)); in r600_cs_check_reg()
1140 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1142 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1145 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1150 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1163 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1175 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1176 track->cb_color_size_idx[tmp] = idx; in r600_cs_check_reg()
1204 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1212 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1213 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1235 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1243 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1244 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1259 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1279 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1280 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1281 track->cb_color_base_last[tmp] = ib[idx]; in r600_cs_check_reg()
1293 track->db_offset = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1294 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1306 track->htile_offset = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1307 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1312 track->htile_surface = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1314 ib[idx] |= 3; in r600_cs_check_reg()
1376 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1385 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1388 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in r600_cs_check_reg()
1391 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_cs_check_reg()
1467 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, in r600_check_texture_resource() argument
1492 word0 = radeon_get_ib_value(p, idx + 0); in r600_check_texture_resource()
1499 word1 = radeon_get_ib_value(p, idx + 1); in r600_check_texture_resource()
1500 word2 = radeon_get_ib_value(p, idx + 2) << 8; in r600_check_texture_resource()
1501 word3 = radeon_get_ib_value(p, idx + 3) << 8; in r600_check_texture_resource()
1502 word4 = radeon_get_ib_value(p, idx + 4); in r600_check_texture_resource()
1503 word5 = radeon_get_ib_value(p, idx + 5); in r600_check_texture_resource()
1608 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in r600_is_safe_reg() argument
1614 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_is_safe_reg()
1620 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_is_safe_reg()
1630 unsigned idx; in r600_packet3_check() local
1638 idx = pkt->idx + 1; in r600_packet3_check()
1639 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()
1653 tmp = radeon_get_ib_value(p, idx + 1); in r600_packet3_check()
1675 ib[idx + 0] = offset; in r600_packet3_check()
1676 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1714 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in r600_packet3_check()
1716 ib[idx+0] = offset; in r600_packet3_check()
1717 ib[idx+1] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1733 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in r600_packet3_check()
1765 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + in r600_packet3_check()
1766 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1768 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); in r600_packet3_check()
1769 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1783 command = radeon_get_ib_value(p, idx+4); in r600_packet3_check()
1801 tmp = radeon_get_ib_value(p, idx) + in r600_packet3_check()
1802 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in r600_packet3_check()
1812 ib[idx] = offset; in r600_packet3_check()
1813 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1831 tmp = radeon_get_ib_value(p, idx+2) + in r600_packet3_check()
1832 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); in r600_packet3_check()
1842 ib[idx+2] = offset; in r600_packet3_check()
1843 ib[idx+3] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1853 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in r600_packet3_check()
1854 radeon_get_ib_value(p, idx + 2) != 0) { in r600_packet3_check()
1860 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1877 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in r600_packet3_check()
1878 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1880 ib[idx+1] = offset & 0xfffffff8; in r600_packet3_check()
1881 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1899 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in r600_packet3_check()
1900 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1902 ib[idx+1] = offset & 0xfffffffc; in r600_packet3_check()
1903 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1917 r = r600_cs_check_reg(p, reg, idx+1+i); in r600_packet3_check()
1933 r = r600_cs_check_reg(p, reg, idx+1+i); in r600_packet3_check()
1955 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { in r600_packet3_check()
1966 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); in r600_packet3_check()
1968 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); in r600_packet3_check()
1979 r = r600_check_texture_resource(p, idx+(i*7)+1, in r600_packet3_check()
1981 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), in r600_packet3_check()
1982 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), in r600_packet3_check()
1986 ib[idx+1+(i*7)+2] += base_offset; in r600_packet3_check()
1987 ib[idx+1+(i*7)+3] += mip_offset; in r600_packet3_check()
1998 offset = radeon_get_ib_value(p, idx+1+(i*7)+0); in r600_packet3_check()
1999 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; in r600_packet3_check()
2004 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; in r600_packet3_check()
2008 ib[idx+1+(i*8)+0] = offset64; in r600_packet3_check()
2009 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in r600_packet3_check()
2105 offset = radeon_get_ib_value(p, idx+1) << 8; in r600_packet3_check()
2117 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
2143 offset = radeon_get_ib_value(p, idx+1); in r600_packet3_check()
2144 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_packet3_check()
2151 ib[idx+1] = offset; in r600_packet3_check()
2152 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2162 offset = radeon_get_ib_value(p, idx+3); in r600_packet3_check()
2163 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_packet3_check()
2170 ib[idx+3] = offset; in r600_packet3_check()
2171 ib[idx+4] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2187 offset = radeon_get_ib_value(p, idx+0); in r600_packet3_check()
2188 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; in r600_packet3_check()
2199 ib[idx+0] = offset; in r600_packet3_check()
2200 ib[idx+1] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2216 offset = radeon_get_ib_value(p, idx+1); in r600_packet3_check()
2217 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_packet3_check()
2224 ib[idx+1] = offset; in r600_packet3_check()
2225 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2228 reg = radeon_get_ib_value(p, idx+1) << 2; in r600_packet3_check()
2229 if (!r600_is_safe_reg(p, reg, idx+1)) in r600_packet3_check()
2240 offset = radeon_get_ib_value(p, idx+3); in r600_packet3_check()
2241 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_packet3_check()
2248 ib[idx+3] = offset; in r600_packet3_check()
2249 ib[idx+4] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2252 reg = radeon_get_ib_value(p, idx+3) << 2; in r600_packet3_check()
2253 if (!r600_is_safe_reg(p, reg, idx+3)) in r600_packet3_check()
2290 r = radeon_cs_packet_parse(p, &pkt, p->idx); in r600_cs_parse()
2296 p->idx += pkt.count + 2; in r600_cs_parse()
2317 } while (p->idx < p->chunk_ib->length_dw); in r600_cs_parse()
2343 unsigned idx; in r600_dma_cs_next_reloc() local
2350 idx = p->dma_reloc_idx; in r600_dma_cs_next_reloc()
2351 if (idx >= p->nrelocs) { in r600_dma_cs_next_reloc()
2353 idx, p->nrelocs); in r600_dma_cs_next_reloc()
2356 *cs_reloc = &p->relocs[idx]; in r600_dma_cs_next_reloc()
2380 u32 idx, idx_value; in r600_dma_cs_parse() local
2385 if (p->idx >= ib_chunk->length_dw) { in r600_dma_cs_parse()
2387 p->idx, ib_chunk->length_dw); in r600_dma_cs_parse()
2390 idx = p->idx; in r600_dma_cs_parse()
2391 header = radeon_get_ib_value(p, idx); in r600_dma_cs_parse()
2404 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2407 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2408 p->idx += count + 5; in r600_dma_cs_parse()
2410 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2411 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_dma_cs_parse()
2413 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2414 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2415 p->idx += count + 3; in r600_dma_cs_parse()
2435 idx_value = radeon_get_ib_value(p, idx + 2); in r600_dma_cs_parse()
2439 src_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2441 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2443 dst_offset = radeon_get_ib_value(p, idx+5); in r600_dma_cs_parse()
2444 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in r600_dma_cs_parse()
2445 ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2446 ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2449 src_offset = radeon_get_ib_value(p, idx+5); in r600_dma_cs_parse()
2450 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in r600_dma_cs_parse()
2451 ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2452 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2454 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2456 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2458 p->idx += 7; in r600_dma_cs_parse()
2461 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2462 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_dma_cs_parse()
2463 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2464 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in r600_dma_cs_parse()
2466 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2467 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2468 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2469 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2470 p->idx += 5; in r600_dma_cs_parse()
2472 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2473 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in r600_dma_cs_parse()
2474 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2475 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; in r600_dma_cs_parse()
2477 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2478 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2479 ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2480 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; in r600_dma_cs_parse()
2481 p->idx += 4; in r600_dma_cs_parse()
2505 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2506 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in r600_dma_cs_parse()
2512 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2513 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in r600_dma_cs_parse()
2514 p->idx += 4; in r600_dma_cs_parse()
2517 p->idx += 1; in r600_dma_cs_parse()
2520 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in r600_dma_cs_parse()
2523 } while (p->idx < p->chunk_ib->length_dw); in r600_dma_cs_parse()