26 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);  in ocelot_irq_unmask()  local
31 	irq_gc_lock(gc);  in ocelot_irq_unmask()
32 	val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) |  in ocelot_irq_unmask()
33 	      irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(1));  in ocelot_irq_unmask()
35 		irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY);  in ocelot_irq_unmask()
38 	irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET);  in ocelot_irq_unmask()
39 	irq_gc_unlock(gc);  in ocelot_irq_unmask()
46 	struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);  in ocelot_irq_handler()  local
47 	u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(0));  in ocelot_irq_handler()
65 	struct irq_chip_generic *gc;  in ocelot_irq_init()  local
87 	gc = irq_get_domain_generic_chip(domain, 0);  in ocelot_irq_init()
88 	gc->reg_base = of_iomap(node, 0);  in ocelot_irq_init()
89 	if (!gc->reg_base) {  in ocelot_irq_init()
95 	gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY;  in ocelot_irq_init()
96 	gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR;  in ocelot_irq_init()
97 	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;  in ocelot_irq_init()
98 	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;  in ocelot_irq_init()
99 	gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;  in ocelot_irq_init()
102 	irq_reg_writel(gc, 0, ICPU_CFG_INTR_INTR_ENA);  in ocelot_irq_init()
103 	irq_reg_writel(gc, 0xffffffff, ICPU_CFG_INTR_INTR_STICKY);  in ocelot_irq_init()
111 	irq_free_generic_chip(gc);  in ocelot_irq_init()