Lines Matching refs:host
258 #define sh_mmcif_host_to_dev(host) (&host->pd->dev) argument
260 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, in sh_mmcif_bitset() argument
263 writel(val | readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitset()
266 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, in sh_mmcif_bitclr() argument
269 writel(~val & readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitclr()
274 struct sh_mmcif_host *host = arg; in sh_mmcif_dma_complete() local
275 struct mmc_request *mrq = host->mrq; in sh_mmcif_dma_complete()
276 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_dma_complete()
284 complete(&host->dma_complete); in sh_mmcif_dma_complete()
287 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) in sh_mmcif_start_dma_rx() argument
289 struct mmc_data *data = host->mrq->data; in sh_mmcif_start_dma_rx()
292 struct dma_chan *chan = host->chan_rx; in sh_mmcif_start_dma_rx()
293 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_start_dma_rx()
300 host->dma_active = true; in sh_mmcif_start_dma_rx()
307 desc->callback_param = host; in sh_mmcif_start_dma_rx()
309 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); in sh_mmcif_start_dma_rx()
319 host->chan_rx = NULL; in sh_mmcif_start_dma_rx()
320 host->dma_active = false; in sh_mmcif_start_dma_rx()
323 chan = host->chan_tx; in sh_mmcif_start_dma_rx()
325 host->chan_tx = NULL; in sh_mmcif_start_dma_rx()
330 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_start_dma_rx()
337 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) in sh_mmcif_start_dma_tx() argument
339 struct mmc_data *data = host->mrq->data; in sh_mmcif_start_dma_tx()
342 struct dma_chan *chan = host->chan_tx; in sh_mmcif_start_dma_tx()
343 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_start_dma_tx()
350 host->dma_active = true; in sh_mmcif_start_dma_tx()
357 desc->callback_param = host; in sh_mmcif_start_dma_tx()
359 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); in sh_mmcif_start_dma_tx()
369 host->chan_tx = NULL; in sh_mmcif_start_dma_tx()
370 host->dma_active = false; in sh_mmcif_start_dma_tx()
373 chan = host->chan_rx; in sh_mmcif_start_dma_tx()
375 host->chan_rx = NULL; in sh_mmcif_start_dma_tx()
380 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_start_dma_tx()
388 sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id) in sh_mmcif_request_dma_pdata() argument
400 static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host, in sh_mmcif_dma_slave_config() argument
407 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); in sh_mmcif_dma_slave_config()
421 static void sh_mmcif_request_dma(struct sh_mmcif_host *host) in sh_mmcif_request_dma() argument
423 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_request_dma()
424 host->dma_active = false; in sh_mmcif_request_dma()
430 host->chan_tx = sh_mmcif_request_dma_pdata(host, in sh_mmcif_request_dma()
432 host->chan_rx = sh_mmcif_request_dma_pdata(host, in sh_mmcif_request_dma()
435 host->chan_tx = dma_request_chan(dev, "tx"); in sh_mmcif_request_dma()
436 if (IS_ERR(host->chan_tx)) in sh_mmcif_request_dma()
437 host->chan_tx = NULL; in sh_mmcif_request_dma()
438 host->chan_rx = dma_request_chan(dev, "rx"); in sh_mmcif_request_dma()
439 if (IS_ERR(host->chan_rx)) in sh_mmcif_request_dma()
440 host->chan_rx = NULL; in sh_mmcif_request_dma()
442 dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx, in sh_mmcif_request_dma()
443 host->chan_rx); in sh_mmcif_request_dma()
445 if (!host->chan_tx || !host->chan_rx || in sh_mmcif_request_dma()
446 sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) || in sh_mmcif_request_dma()
447 sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM)) in sh_mmcif_request_dma()
453 if (host->chan_tx) in sh_mmcif_request_dma()
454 dma_release_channel(host->chan_tx); in sh_mmcif_request_dma()
455 if (host->chan_rx) in sh_mmcif_request_dma()
456 dma_release_channel(host->chan_rx); in sh_mmcif_request_dma()
457 host->chan_tx = host->chan_rx = NULL; in sh_mmcif_request_dma()
460 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) in sh_mmcif_release_dma() argument
462 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_release_dma()
464 if (host->chan_tx) { in sh_mmcif_release_dma()
465 struct dma_chan *chan = host->chan_tx; in sh_mmcif_release_dma()
466 host->chan_tx = NULL; in sh_mmcif_release_dma()
469 if (host->chan_rx) { in sh_mmcif_release_dma()
470 struct dma_chan *chan = host->chan_rx; in sh_mmcif_release_dma()
471 host->chan_rx = NULL; in sh_mmcif_release_dma()
475 host->dma_active = false; in sh_mmcif_release_dma()
478 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) in sh_mmcif_clock_control() argument
480 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_clock_control()
483 unsigned int current_clk = clk_get_rate(host->clk); in sh_mmcif_clock_control()
486 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
487 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); in sh_mmcif_clock_control()
492 if (host->clkdiv_map) { in sh_mmcif_clock_control()
500 if (!((1 << i) & host->clkdiv_map)) in sh_mmcif_clock_control()
509 freq = clk_round_rate(host->clk, clk * div); in sh_mmcif_clock_control()
524 clk_set_rate(host->clk, best_freq); in sh_mmcif_clock_control()
532 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); in sh_mmcif_clock_control()
533 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
536 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) in sh_mmcif_sync_reset() argument
540 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); in sh_mmcif_sync_reset()
542 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); in sh_mmcif_sync_reset()
543 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); in sh_mmcif_sync_reset()
544 if (host->ccs_enable) in sh_mmcif_sync_reset()
546 if (host->clk_ctrl2_enable) in sh_mmcif_sync_reset()
547 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); in sh_mmcif_sync_reset()
548 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | in sh_mmcif_sync_reset()
551 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); in sh_mmcif_sync_reset()
554 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) in sh_mmcif_error_manage() argument
556 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_error_manage()
560 host->sd_error = false; in sh_mmcif_error_manage()
562 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); in sh_mmcif_error_manage()
563 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); in sh_mmcif_error_manage()
568 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); in sh_mmcif_error_manage()
569 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); in sh_mmcif_error_manage()
571 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) in sh_mmcif_error_manage()
581 sh_mmcif_sync_reset(host); in sh_mmcif_error_manage()
588 host->state, host->wait_for); in sh_mmcif_error_manage()
592 host->state, host->wait_for); in sh_mmcif_error_manage()
596 host->state, host->wait_for); in sh_mmcif_error_manage()
602 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) in sh_mmcif_next_block() argument
604 struct mmc_data *data = host->mrq->data; in sh_mmcif_next_block()
606 host->sg_blkidx += host->blocksize; in sh_mmcif_next_block()
609 BUG_ON(host->sg_blkidx > data->sg->length); in sh_mmcif_next_block()
611 if (host->sg_blkidx == data->sg->length) { in sh_mmcif_next_block()
612 host->sg_blkidx = 0; in sh_mmcif_next_block()
613 if (++host->sg_idx < data->sg_len) in sh_mmcif_next_block()
614 host->pio_ptr = sg_virt(++data->sg); in sh_mmcif_next_block()
616 host->pio_ptr = p; in sh_mmcif_next_block()
619 return host->sg_idx != data->sg_len; in sh_mmcif_next_block()
622 static void sh_mmcif_single_read(struct sh_mmcif_host *host, in sh_mmcif_single_read() argument
625 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_single_read()
628 host->wait_for = MMCIF_WAIT_FOR_READ; in sh_mmcif_single_read()
631 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_single_read()
634 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) in sh_mmcif_read_block() argument
636 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_read_block()
637 struct mmc_data *data = host->mrq->data; in sh_mmcif_read_block()
641 if (host->sd_error) { in sh_mmcif_read_block()
642 data->error = sh_mmcif_error_manage(host); in sh_mmcif_read_block()
647 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_read_block()
648 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); in sh_mmcif_read_block()
651 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); in sh_mmcif_read_block()
652 host->wait_for = MMCIF_WAIT_FOR_READ_END; in sh_mmcif_read_block()
657 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, in sh_mmcif_multi_read() argument
665 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_multi_read()
668 host->wait_for = MMCIF_WAIT_FOR_MREAD; in sh_mmcif_multi_read()
669 host->sg_idx = 0; in sh_mmcif_multi_read()
670 host->sg_blkidx = 0; in sh_mmcif_multi_read()
671 host->pio_ptr = sg_virt(data->sg); in sh_mmcif_multi_read()
673 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_multi_read()
676 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) in sh_mmcif_mread_block() argument
678 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_mread_block()
679 struct mmc_data *data = host->mrq->data; in sh_mmcif_mread_block()
680 u32 *p = host->pio_ptr; in sh_mmcif_mread_block()
683 if (host->sd_error) { in sh_mmcif_mread_block()
684 data->error = sh_mmcif_error_manage(host); in sh_mmcif_mread_block()
691 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_mread_block()
692 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); in sh_mmcif_mread_block()
694 if (!sh_mmcif_next_block(host, p)) in sh_mmcif_mread_block()
697 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_mread_block()
702 static void sh_mmcif_single_write(struct sh_mmcif_host *host, in sh_mmcif_single_write() argument
705 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_single_write()
708 host->wait_for = MMCIF_WAIT_FOR_WRITE; in sh_mmcif_single_write()
711 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_single_write()
714 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) in sh_mmcif_write_block() argument
716 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_write_block()
717 struct mmc_data *data = host->mrq->data; in sh_mmcif_write_block()
721 if (host->sd_error) { in sh_mmcif_write_block()
722 data->error = sh_mmcif_error_manage(host); in sh_mmcif_write_block()
727 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_write_block()
728 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); in sh_mmcif_write_block()
731 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); in sh_mmcif_write_block()
732 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; in sh_mmcif_write_block()
737 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, in sh_mmcif_multi_write() argument
745 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_multi_write()
748 host->wait_for = MMCIF_WAIT_FOR_MWRITE; in sh_mmcif_multi_write()
749 host->sg_idx = 0; in sh_mmcif_multi_write()
750 host->sg_blkidx = 0; in sh_mmcif_multi_write()
751 host->pio_ptr = sg_virt(data->sg); in sh_mmcif_multi_write()
753 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_multi_write()
756 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) in sh_mmcif_mwrite_block() argument
758 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_mwrite_block()
759 struct mmc_data *data = host->mrq->data; in sh_mmcif_mwrite_block()
760 u32 *p = host->pio_ptr; in sh_mmcif_mwrite_block()
763 if (host->sd_error) { in sh_mmcif_mwrite_block()
764 data->error = sh_mmcif_error_manage(host); in sh_mmcif_mwrite_block()
771 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_mwrite_block()
772 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); in sh_mmcif_mwrite_block()
774 if (!sh_mmcif_next_block(host, p)) in sh_mmcif_mwrite_block()
777 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_mwrite_block()
782 static void sh_mmcif_get_response(struct sh_mmcif_host *host, in sh_mmcif_get_response() argument
786 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); in sh_mmcif_get_response()
787 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); in sh_mmcif_get_response()
788 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); in sh_mmcif_get_response()
789 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); in sh_mmcif_get_response()
791 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); in sh_mmcif_get_response()
794 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, in sh_mmcif_get_cmd12response() argument
797 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); in sh_mmcif_get_cmd12response()
800 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, in sh_mmcif_set_cmd() argument
803 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_set_cmd()
832 switch (host->bus_width) { in sh_mmcif_set_cmd()
846 switch (host->timing) { in sh_mmcif_set_cmd()
865 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, in sh_mmcif_set_cmd()
883 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, in sh_mmcif_data_trans() argument
886 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_data_trans()
890 sh_mmcif_multi_read(host, mrq); in sh_mmcif_data_trans()
893 sh_mmcif_multi_write(host, mrq); in sh_mmcif_data_trans()
896 sh_mmcif_single_write(host, mrq); in sh_mmcif_data_trans()
900 sh_mmcif_single_read(host, mrq); in sh_mmcif_data_trans()
908 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, in sh_mmcif_start_cmd() argument
921 if (host->ccs_enable) in sh_mmcif_start_cmd()
925 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); in sh_mmcif_start_cmd()
926 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, in sh_mmcif_start_cmd()
929 opc = sh_mmcif_set_cmd(host, mrq); in sh_mmcif_start_cmd()
931 if (host->ccs_enable) in sh_mmcif_start_cmd()
932 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); in sh_mmcif_start_cmd()
934 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); in sh_mmcif_start_cmd()
935 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); in sh_mmcif_start_cmd()
937 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); in sh_mmcif_start_cmd()
939 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_start_cmd()
940 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); in sh_mmcif_start_cmd()
942 host->wait_for = MMCIF_WAIT_FOR_CMD; in sh_mmcif_start_cmd()
943 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_start_cmd()
944 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_start_cmd()
947 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, in sh_mmcif_stop_cmd() argument
950 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_stop_cmd()
954 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); in sh_mmcif_stop_cmd()
957 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); in sh_mmcif_stop_cmd()
961 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_stop_cmd()
965 host->wait_for = MMCIF_WAIT_FOR_STOP; in sh_mmcif_stop_cmd()
970 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_request() local
971 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_request()
974 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_request()
975 if (host->state != STATE_IDLE) { in sh_mmcif_request()
977 __func__, host->state); in sh_mmcif_request()
978 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_request()
984 host->state = STATE_REQUEST; in sh_mmcif_request()
985 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_request()
987 host->mrq = mrq; in sh_mmcif_request()
989 sh_mmcif_start_cmd(host, mrq); in sh_mmcif_request()
992 static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) in sh_mmcif_clk_setup() argument
994 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_clk_setup()
996 if (host->mmc->f_max) { in sh_mmcif_clk_setup()
999 f_max = host->mmc->f_max; in sh_mmcif_clk_setup()
1001 f_min = clk_round_rate(host->clk, f_min_old / 2); in sh_mmcif_clk_setup()
1010 host->clkdiv_map = 0x3ff; in sh_mmcif_clk_setup()
1012 host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map)); in sh_mmcif_clk_setup()
1013 host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map)); in sh_mmcif_clk_setup()
1015 unsigned int clk = clk_get_rate(host->clk); in sh_mmcif_clk_setup()
1017 host->mmc->f_max = clk / 2; in sh_mmcif_clk_setup()
1018 host->mmc->f_min = clk / 512; in sh_mmcif_clk_setup()
1022 host->mmc->f_max, host->mmc->f_min); in sh_mmcif_clk_setup()
1027 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_set_ios() local
1028 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_set_ios()
1031 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_set_ios()
1032 if (host->state != STATE_IDLE) { in sh_mmcif_set_ios()
1034 __func__, host->state); in sh_mmcif_set_ios()
1035 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_set_ios()
1039 host->state = STATE_IOS; in sh_mmcif_set_ios()
1040 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_set_ios()
1046 if (!host->power) { in sh_mmcif_set_ios()
1047 clk_prepare_enable(host->clk); in sh_mmcif_set_ios()
1049 sh_mmcif_sync_reset(host); in sh_mmcif_set_ios()
1050 sh_mmcif_request_dma(host); in sh_mmcif_set_ios()
1051 host->power = true; in sh_mmcif_set_ios()
1057 if (host->power) { in sh_mmcif_set_ios()
1058 sh_mmcif_clock_control(host, 0); in sh_mmcif_set_ios()
1059 sh_mmcif_release_dma(host); in sh_mmcif_set_ios()
1061 clk_disable_unprepare(host->clk); in sh_mmcif_set_ios()
1062 host->power = false; in sh_mmcif_set_ios()
1066 sh_mmcif_clock_control(host, ios->clock); in sh_mmcif_set_ios()
1070 host->timing = ios->timing; in sh_mmcif_set_ios()
1071 host->bus_width = ios->bus_width; in sh_mmcif_set_ios()
1072 host->state = STATE_IDLE; in sh_mmcif_set_ios()
1081 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) in sh_mmcif_end_cmd() argument
1083 struct mmc_command *cmd = host->mrq->cmd; in sh_mmcif_end_cmd()
1084 struct mmc_data *data = host->mrq->data; in sh_mmcif_end_cmd()
1085 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_end_cmd()
1088 if (host->sd_error) { in sh_mmcif_end_cmd()
1096 cmd->error = sh_mmcif_error_manage(host); in sh_mmcif_end_cmd()
1101 host->sd_error = false; in sh_mmcif_end_cmd()
1109 sh_mmcif_get_response(host, cmd); in sh_mmcif_end_cmd()
1118 init_completion(&host->dma_complete); in sh_mmcif_end_cmd()
1121 if (host->chan_rx) in sh_mmcif_end_cmd()
1122 sh_mmcif_start_dma_rx(host); in sh_mmcif_end_cmd()
1124 if (host->chan_tx) in sh_mmcif_end_cmd()
1125 sh_mmcif_start_dma_tx(host); in sh_mmcif_end_cmd()
1128 if (!host->dma_active) { in sh_mmcif_end_cmd()
1129 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); in sh_mmcif_end_cmd()
1134 time = wait_for_completion_interruptible_timeout(&host->dma_complete, in sh_mmcif_end_cmd()
1135 host->timeout); in sh_mmcif_end_cmd()
1138 dma_unmap_sg(host->chan_rx->device->dev, in sh_mmcif_end_cmd()
1142 dma_unmap_sg(host->chan_tx->device->dev, in sh_mmcif_end_cmd()
1146 if (host->sd_error) { in sh_mmcif_end_cmd()
1147 dev_err(host->mmc->parent, in sh_mmcif_end_cmd()
1150 data->error = sh_mmcif_error_manage(host); in sh_mmcif_end_cmd()
1152 dev_err(host->mmc->parent, "DMA timeout!\n"); in sh_mmcif_end_cmd()
1155 dev_err(host->mmc->parent, in sh_mmcif_end_cmd()
1159 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, in sh_mmcif_end_cmd()
1161 host->dma_active = false; in sh_mmcif_end_cmd()
1167 dmaengine_terminate_all(host->chan_rx); in sh_mmcif_end_cmd()
1169 dmaengine_terminate_all(host->chan_tx); in sh_mmcif_end_cmd()
1177 struct sh_mmcif_host *host = dev_id; in sh_mmcif_irqt() local
1179 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_irqt()
1184 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_irqt()
1185 wait_work = host->wait_for; in sh_mmcif_irqt()
1186 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_irqt()
1188 cancel_delayed_work_sync(&host->timeout_work); in sh_mmcif_irqt()
1190 mutex_lock(&host->thread_lock); in sh_mmcif_irqt()
1192 mrq = host->mrq; in sh_mmcif_irqt()
1195 host->state, host->wait_for); in sh_mmcif_irqt()
1196 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1207 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1211 wait = sh_mmcif_end_cmd(host); in sh_mmcif_irqt()
1215 wait = sh_mmcif_mread_block(host); in sh_mmcif_irqt()
1219 wait = sh_mmcif_read_block(host); in sh_mmcif_irqt()
1223 wait = sh_mmcif_mwrite_block(host); in sh_mmcif_irqt()
1227 wait = sh_mmcif_write_block(host); in sh_mmcif_irqt()
1230 if (host->sd_error) { in sh_mmcif_irqt()
1231 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_irqt()
1235 sh_mmcif_get_cmd12response(host, mrq->stop); in sh_mmcif_irqt()
1240 if (host->sd_error) { in sh_mmcif_irqt()
1241 mrq->data->error = sh_mmcif_error_manage(host); in sh_mmcif_irqt()
1250 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_irqt()
1252 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1256 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { in sh_mmcif_irqt()
1263 sh_mmcif_stop_cmd(host, mrq); in sh_mmcif_irqt()
1265 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_irqt()
1266 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1272 host->wait_for = MMCIF_WAIT_FOR_REQUEST; in sh_mmcif_irqt()
1273 host->state = STATE_IDLE; in sh_mmcif_irqt()
1274 host->mrq = NULL; in sh_mmcif_irqt()
1275 mmc_request_done(host->mmc, mrq); in sh_mmcif_irqt()
1277 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1284 struct sh_mmcif_host *host = dev_id; in sh_mmcif_intr() local
1285 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_intr()
1288 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); in sh_mmcif_intr()
1289 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); in sh_mmcif_intr()
1290 if (host->ccs_enable) in sh_mmcif_intr()
1291 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); in sh_mmcif_intr()
1293 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); in sh_mmcif_intr()
1294 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); in sh_mmcif_intr()
1301 host->sd_error = true; in sh_mmcif_intr()
1305 if (!host->mrq) in sh_mmcif_intr()
1307 if (!host->dma_active) in sh_mmcif_intr()
1309 else if (host->sd_error) in sh_mmcif_intr()
1310 sh_mmcif_dma_complete(host); in sh_mmcif_intr()
1321 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); in sh_mmcif_timeout_work() local
1322 struct mmc_request *mrq = host->mrq; in sh_mmcif_timeout_work()
1323 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_timeout_work()
1326 if (host->dying) in sh_mmcif_timeout_work()
1330 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_timeout_work()
1331 if (host->state == STATE_IDLE) { in sh_mmcif_timeout_work()
1332 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_timeout_work()
1337 host->wait_for, mrq->cmd->opcode); in sh_mmcif_timeout_work()
1339 host->state = STATE_TIMEOUT; in sh_mmcif_timeout_work()
1340 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_timeout_work()
1346 switch (host->wait_for) { in sh_mmcif_timeout_work()
1348 mrq->cmd->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1351 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1359 mrq->data->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1365 host->state = STATE_IDLE; in sh_mmcif_timeout_work()
1366 host->wait_for = MMCIF_WAIT_FOR_REQUEST; in sh_mmcif_timeout_work()
1367 host->mrq = NULL; in sh_mmcif_timeout_work()
1368 mmc_request_done(host->mmc, mrq); in sh_mmcif_timeout_work()
1371 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) in sh_mmcif_init_ocr() argument
1373 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_init_ocr()
1375 struct mmc_host *mmc = host->mmc; in sh_mmcif_init_ocr()
1392 struct sh_mmcif_host *host; in sh_mmcif_probe() local
1415 host = mmc_priv(mmc); in sh_mmcif_probe()
1416 host->mmc = mmc; in sh_mmcif_probe()
1417 host->addr = reg; in sh_mmcif_probe()
1418 host->timeout = msecs_to_jiffies(10000); in sh_mmcif_probe()
1419 host->ccs_enable = true; in sh_mmcif_probe()
1420 host->clk_ctrl2_enable = false; in sh_mmcif_probe()
1422 host->pd = pdev; in sh_mmcif_probe()
1424 spin_lock_init(&host->lock); in sh_mmcif_probe()
1427 sh_mmcif_init_ocr(host); in sh_mmcif_probe()
1441 platform_set_drvdata(pdev, host); in sh_mmcif_probe()
1443 host->clk = devm_clk_get(dev, NULL); in sh_mmcif_probe()
1444 if (IS_ERR(host->clk)) { in sh_mmcif_probe()
1445 ret = PTR_ERR(host->clk); in sh_mmcif_probe()
1450 ret = clk_prepare_enable(host->clk); in sh_mmcif_probe()
1454 sh_mmcif_clk_setup(host); in sh_mmcif_probe()
1457 host->power = false; in sh_mmcif_probe()
1463 INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); in sh_mmcif_probe()
1465 sh_mmcif_sync_reset(host); in sh_mmcif_probe()
1466 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_probe()
1470 sh_mmcif_irqt, 0, name, host); in sh_mmcif_probe()
1478 0, "sh_mmc:int", host); in sh_mmcif_probe()
1485 mutex_init(&host->thread_lock); in sh_mmcif_probe()
1494 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, in sh_mmcif_probe()
1495 clk_get_rate(host->clk) / 1000000UL); in sh_mmcif_probe()
1498 clk_disable_unprepare(host->clk); in sh_mmcif_probe()
1502 clk_disable_unprepare(host->clk); in sh_mmcif_probe()
1512 struct sh_mmcif_host *host = platform_get_drvdata(pdev); in sh_mmcif_remove() local
1514 host->dying = true; in sh_mmcif_remove()
1515 clk_prepare_enable(host->clk); in sh_mmcif_remove()
1520 mmc_remove_host(host->mmc); in sh_mmcif_remove()
1521 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_remove()
1528 cancel_delayed_work_sync(&host->timeout_work); in sh_mmcif_remove()
1530 clk_disable_unprepare(host->clk); in sh_mmcif_remove()
1531 mmc_free_host(host->mmc); in sh_mmcif_remove()
1541 struct sh_mmcif_host *host = dev_get_drvdata(dev); in sh_mmcif_suspend() local
1544 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_suspend()